{"doi":"10.1109/IPDPS.2011.153","quality_controlled":"1","status":"public","date_created":"2018-04-03T15:05:52Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"last_name":"Grad","full_name":"Grad, Mariusz","first_name":"Mariusz"},{"first_name":"Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian"}],"year":"2011","user_id":"15278","citation":{"ama":"Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>. IEEE Computer Society; 2011:278-285. doi:<a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>","mla":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, IEEE Computer Society, 2011, pp. 278–85, doi:<a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>.","bibtex":"@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}, DOI={<a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>}, booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011}, pages={278–285} }","ieee":"M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 2011, pp. 278–285, doi: <a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>.","chicago":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” In <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 278–85. IEEE Computer Society, 2011. <a href=\"https://doi.org/10.1109/IPDPS.2011.153\">https://doi.org/10.1109/IPDPS.2011.153</a>.","apa":"Grad, M., &#38; Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 278–285. <a href=\"https://doi.org/10.1109/IPDPS.2011.153\">https://doi.org/10.1109/IPDPS.2011.153</a>","short":"M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285."},"type":"conference","publication":"Proc. Reconfigurable Architectures Workshop (RAW)","date_updated":"2023-09-26T13:44:39Z","page":"278-285","_id":"2198","title":"Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture","language":[{"iso":"eng"}],"publisher":"IEEE Computer Society"}