{"date_created":"2017-10-17T12:41:35Z","file_date_updated":"2018-03-21T10:36:08Z","abstract":[{"text":"Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.","lang":"eng"}],"has_accepted_license":"1","project":[{"_id":"1","name":"SFB 901"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}],"page":"112--122","file":[{"file_id":"1511","file_name":"222-1-s2.0-S0045790616300684-main.pdf","success":1,"date_updated":"2018-03-21T10:36:08Z","date_created":"2018-03-21T10:36:08Z","creator":"florida","file_size":931048,"access_level":"closed","content_type":"application/pdf","relation":"main_file"}],"doi":"10.1016/j.compeleceng.2016.04.005","ddc":["040"],"user_id":"477","citation":{"chicago":"Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” <i>Computers &#38; Electrical Engineering</i>, 2016, 112--122. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">https://doi.org/10.1016/j.compeleceng.2016.04.005</a>.","short":"T. Wiersema, A. Bockhorn, M. Platzner, Computers &#38; Electrical Engineering (2016) 112--122.","apa":"Wiersema, T., Bockhorn, A., &#38; Platzner, M. (2016). An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. <i>Computers &#38; Electrical Engineering</i>, 112--122. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">https://doi.org/10.1016/j.compeleceng.2016.04.005</a>","ama":"Wiersema T, Bockhorn A, Platzner M. An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. <i>Computers &#38; Electrical Engineering</i>. 2016:112--122. doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>","bibtex":"@article{Wiersema_Bockhorn_Platzner_2016, title={An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}, DOI={<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>}, journal={Computers &#38; Electrical Engineering}, publisher={Elsevier}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2016}, pages={112--122} }","mla":"Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” <i>Computers &#38; Electrical Engineering</i>, Elsevier, 2016, pp. 112--122, doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>.","ieee":"T. Wiersema, A. Bockhorn, and M. Platzner, “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip,” <i>Computers &#38; Electrical Engineering</i>, pp. 112--122, 2016."},"title":"An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip","_id":"222","department":[{"_id":"78"}],"publisher":"Elsevier","author":[{"full_name":"Wiersema, Tobias","id":"3118","last_name":"Wiersema","first_name":"Tobias"},{"first_name":"Arne","full_name":"Bockhorn, Arne","last_name":"Bockhorn"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"year":"2016","status":"public","date_updated":"2022-01-06T06:55:29Z","type":"journal_article","publication":"Computers & Electrical Engineering","language":[{"iso":"eng"}]}