--- res: bibo_abstract: - Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. @eng bibo_authorlist: - foaf_Person: foaf_givenName: Tobias foaf_name: Schumacher, Tobias foaf_surname: Schumacher - foaf_Person: foaf_givenName: Christian foaf_name: Plessl, Christian foaf_surname: Plessl foaf_workInfoHomepage: http://www.librecat.org/personId=16153 orcid: 0000-0001-5728-9982 - foaf_Person: foaf_givenName: Marco foaf_name: Platzner, Marco foaf_surname: Platzner foaf_workInfoHomepage: http://www.librecat.org/personId=398 bibo_doi: 10.1109/FCCM.2009.25 dct_date: 2009^xs_gYear dct_isPartOf: - http://id.crossref.org/issn/978-1-4244-4450-2 dct_language: eng dct_publisher: IEEE Computer Society@ dct_subject: - IMORC - interconnect - performance dct_title: 'IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing@' ...