---
res:
  bibo_abstract:
  - Fault effect simulation is a well-established technique for the qualification
    of robust embedded software and hardware as required by different safety standards.
    Our article introduces a Virtual Prototype based approach for the fault analysis
    and fast simulation of a set of automatically generated and target compiled software
    programs. The approach scales to different RISC-V ISA standard subset configurations
    and is based on an instruction and hardware register coverage for automatic fault
    injections of permanent and transient bitflips. The analysis of each software
    binary evaluates its opcode type and register access coverage including the addressed
    memory space. Based on this information dedicated sets of fault injected hardware
    models, i.e., mutants, are generated. The simulation of all mutants conducted
    with the different binaries finally identifies the cases with a normal termination
    though executed on a faulty hardware model. They are identified as a subject for
    further investigations and improvements by the implementation of additional hardware
    or software safety countermeasures. Our final evaluation results with automatic
    C code generation, compilation, analysis, and simulation show that QEMU provides
    an adequate efficient platform, which also scales to more complex scenarios.@eng
  bibo_authorlist:
  - foaf_Person:
      foaf_givenName: Peer
      foaf_name: Adelt, Peer
      foaf_surname: Adelt
      foaf_workInfoHomepage: http://www.librecat.org/personId=5603
  - foaf_Person:
      foaf_givenName: Bastian
      foaf_name: Koppelmann, Bastian
      foaf_surname: Koppelmann
      foaf_workInfoHomepage: http://www.librecat.org/personId=25260
  - foaf_Person:
      foaf_givenName: Wolfgang
      foaf_name: Müller, Wolfgang
      foaf_surname: Müller
      foaf_workInfoHomepage: http://www.librecat.org/personId=16243
  - foaf_Person:
      foaf_givenName: Christoph
      foaf_name: Scheytt, Christoph
      foaf_surname: Scheytt
      foaf_workInfoHomepage: http://www.librecat.org/personId=37144
  dct_date: 2020^xs_gYear
  dct_language: eng
  dct_title: A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware
    Architectures@
...