---
_id: '24027'
abstract:
- lang: eng
  text: Fault effect simulation is a well-established technique for the qualification
    of robust embedded software and hardware as required by different safety standards.
    Our article introduces a Virtual Prototype based approach for the fault analysis
    and fast simulation of a set of automatically generated and target compiled software
    programs. The approach scales to different RISC-V ISA standard subset configurations
    and is based on an instruction and hardware register coverage for automatic fault
    injections of permanent and transient bitflips. The analysis of each software
    binary evaluates its opcode type and register access coverage including the addressed
    memory space. Based on this information dedicated sets of fault injected hardware
    models, i.e., mutants, are generated. The simulation of all mutants conducted
    with the different binaries finally identifies the cases with a normal termination
    though executed on a faulty hardware model. They are identified as a subject for
    further investigations and improvements by the implementation of additional hardware
    or software safety countermeasures. Our final evaluation results with automatic
    C code generation, compilation, analysis, and simulation show that QEMU provides
    an adequate efficient platform, which also scales to more complex scenarios.
author:
- first_name: Peer
  full_name: Adelt, Peer
  id: '5603'
  last_name: Adelt
- first_name: Bastian
  full_name: Koppelmann, Bastian
  id: '25260'
  last_name: Koppelmann
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
citation:
  ama: 'Adelt P, Koppelmann B, Müller W, Scheytt C. A Scalable Platform for QEMU Based
    Fault Effect Analysis for RISC-V Hardware Architectures. In: <i>MBMV 2020 - Methods
    and Description Languages for Modelling and Verification of Circuits and Systems;
    GMM/ITG/GI-Workshop</i>. ; 2020.'
  apa: Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2020). A Scalable
    Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.
    <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification
    of Circuits and Systems; GMM/ITG/GI-Workshop</i>.
  bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2020, place={Stuttgart,
    DE}, title={A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V
    Hardware Architectures}, booktitle={MBMV 2020 - Methods and Description Languages
    for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop},
    author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt,
    Christoph}, year={2020} }'
  chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt.
    “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware
    Architectures.” In <i>MBMV 2020 - Methods and Description Languages for Modelling
    and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. Stuttgart,
    DE, 2020.
  ieee: P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for
    QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.
  mla: Adelt, Peer, et al. “A Scalable Platform for QEMU Based Fault Effect Analysis
    for RISC-V Hardware Architectures.” <i>MBMV 2020 - Methods and Description Languages
    for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>,
    2020.
  short: 'P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods
    and Description Languages for Modelling and Verification of Circuits and Systems;
    GMM/ITG/GI-Workshop, Stuttgart, DE, 2020.'
date_created: 2021-09-09T11:50:19Z
date_updated: 2022-01-06T06:56:06Z
department:
- _id: '58'
language:
- iso: eng
place: Stuttgart, DE
publication: MBMV 2020 - Methods and Description Languages for Modelling and Verification
  of Circuits and Systems; GMM/ITG/GI-Workshop
related_material:
  link:
  - relation: confirmation
    url: https://ieeexplore.ieee.org/document/9094540
status: public
title: A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware
  Architectures
type: conference
user_id: '15931'
year: '2020'
...