---
res:
  bibo_abstract:
  - Embedded systems require a high energy efficiency in combination with an optimized
    performance. As such, Bit Manipulation Instructions (BMIs) were introduced for
    x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled
    software for various applications. Though the RISC-V platform is meanwhile widely
    accepted for embedded systems application, its instruction set architecture (ISA)
    currently still supports only two basic BMIs.We introduce ten advanced BMIs for
    the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized
    for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions
    are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket
    CPU hardware extensions show that RISC-V BMI extensions have no negative impact
    on the critical path of the execution pipeline. Our software evaluations show
    that we can, for example, expect a significant impact for time and power consuming
    cryptographic applications.@eng
  bibo_authorlist:
  - foaf_Person:
      foaf_givenName: Bastian
      foaf_name: Koppelmann, Bastian
      foaf_surname: Koppelmann
      foaf_workInfoHomepage: http://www.librecat.org/personId=25260
  - foaf_Person:
      foaf_givenName: Peer
      foaf_name: Adelt, Peer
      foaf_surname: Adelt
      foaf_workInfoHomepage: http://www.librecat.org/personId=5603
  - foaf_Person:
      foaf_givenName: Wolfgang
      foaf_name: Müller, Wolfgang
      foaf_surname: Müller
      foaf_workInfoHomepage: http://www.librecat.org/personId=16243
  - foaf_Person:
      foaf_givenName: Christoph
      foaf_name: Scheytt, Christoph
      foaf_surname: Scheytt
      foaf_workInfoHomepage: http://www.librecat.org/personId=37144
  bibo_doi: 10.1109/PATMOS.2019.8862170
  dct_date: 2019^xs_gYear
  dct_language: eng
  dct_title: RISC-V Extensions for Bit Manipulation Instructions@
...