[{"publication":"Microprocessors and Microsystems","user_id":"24135","intvolume":"        29","department":[{"_id":"518"},{"_id":"78"}],"issue":"2-3","keyword":["FPGA","reconfigurable computing","co-simulation","Zippy"],"volume":29,"publisher":"Elsevier","status":"public","author":[{"last_name":"Enzler","full_name":"Enzler, Rolf","first_name":"Rolf"},{"last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"_id":"2412","year":"2005","date_created":"2018-04-17T14:36:10Z","citation":{"chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i> 29, no. 2–3 (2005): 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>.","apa":"Enzler, R., Plessl, C., &#38; Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>, <i>29</i>(2–3), 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>","short":"R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.","mla":"Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>.","bibtex":"@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }","ieee":"R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, pp. 63–73, 2005.","ama":"Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>. 2005;29(2-3):63-73. doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>"},"abstract":[{"text":" Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors."}],"date_updated":"2019-01-03T13:13:10Z","title":"System-level performance evaluation of reconfigurable processors","doi":"10.1016/j.micpro.2004.06.004","type":"journal_article","page":"63-73"}]