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<titleInfo><title>Current and Future RISC-V Activities for Virtual Prototyping and Chip Design</title></titleInfo>





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  <namePart type="family">Adelt</namePart>
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  <namePart type="family">Koppelmann</namePart>
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<originInfo><dateIssued encoding="w3cdtf">2018</dateIssued><place><placeTerm type="text">Munich, DE</placeTerm></place>
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<relatedItem type="host"><titleInfo><title>International Workshop on RISC-V Research Activities</title></titleInfo>
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<chicago>Adelt, Peer, Bastian Koppelmann, and Wolfgang Müller. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” &lt;i&gt;International Workshop on RISC-V Research Activities&lt;/i&gt; Presentation (2018).</chicago>
<ama>Adelt P, Koppelmann B, Müller W. Current and Future RISC-V Activities for Virtual Prototyping and Chip Design. &lt;i&gt;International Workshop on RISC-V Research Activities&lt;/i&gt;. 2018;Presentation.</ama>
<short>P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research Activities Presentation (2018).</short>
<bibtex>@article{Adelt_Koppelmann_Müller_2018, title={Current and Future RISC-V Activities for Virtual Prototyping and Chip Design}, volume={Presentation}, journal={International Workshop on RISC-V Research Activities}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang}, year={2018} }</bibtex>
<apa>Adelt, P., Koppelmann, B., &amp;#38; Müller, W. (2018). Current and Future RISC-V Activities for Virtual Prototyping and Chip Design. &lt;i&gt;International Workshop on RISC-V Research Activities&lt;/i&gt;, &lt;i&gt;Presentation&lt;/i&gt;.</apa>
<mla>Adelt, Peer, et al. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” &lt;i&gt;International Workshop on RISC-V Research Activities&lt;/i&gt;, vol. Presentation, 2018.</mla>
<ieee>P. Adelt, B. Koppelmann, and W. Müller, “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design,” &lt;i&gt;International Workshop on RISC-V Research Activities&lt;/i&gt;, vol. Presentation, 2018.</ieee>
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