{"date_created":"2021-09-13T07:38:03Z","user_id":"15931","citation":{"bibtex":"@inproceedings{Wu_Hussain_Abughannam_Müller_Scheytt_Ecker_2018, place={Italy/Taormina}, title={Analog fault simulation automation at schematic level with random sampling techniques}, DOI={<a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>}, booktitle={2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) }, publisher={IEEE}, author={Wu, Liang and Hussain, Mohammad Khizer and Abughannam, Saed and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang}, year={2018} }","chicago":"Wu, Liang, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, and Wolfgang Ecker. “Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques.” In <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>. Italy/Taormina: IEEE, 2018. <a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">https://doi.org/10.1109/DTIS.2018.8368549</a>.","short":"L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.","mla":"Wu, Liang, et al. “Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques.” <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>.","ama":"Wu L, Hussain MK, Abughannam S, Müller W, Scheytt C, Ecker W. Analog fault simulation automation at schematic level with random sampling techniques. In: <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>","ieee":"L. Wu, M. K. Hussain, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “Analog fault simulation automation at schematic level with random sampling techniques,” 2018, doi: <a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>.","apa":"Wu, L., Hussain, M. K., Abughannam, S., Müller, W., Scheytt, C., &#38; Ecker, W. (2018). Analog fault simulation automation at schematic level with random sampling techniques. <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>. <a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">https://doi.org/10.1109/DTIS.2018.8368549</a>"},"related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/8368549","relation":"confirmation"}]},"title":"Analog fault simulation automation at schematic level with random sampling techniques","_id":"24196","department":[{"_id":"58"}],"abstract":[{"lang":"eng","text":"This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation."}],"author":[{"last_name":"Wu","id":"30401","full_name":"Wu, Liang","first_name":"Liang"},{"last_name":"Hussain","full_name":"Hussain, Mohammad Khizer","first_name":"Mohammad Khizer"},{"full_name":"Abughannam, Saed","last_name":"Abughannam","id":"37628","first_name":"Saed"},{"id":"16243","last_name":"Müller","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"id":"37144","last_name":"Scheytt","full_name":"Scheytt, Christoph","first_name":"Christoph"},{"first_name":"Wolfgang","full_name":"Ecker, Wolfgang","last_name":"Ecker"}],"publisher":"IEEE","year":"2018","place":"Italy/Taormina","status":"public","date_updated":"2022-01-06T06:56:09Z","type":"conference","publication":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) ","conference":{"start_date":"2018.04.09","end_date":"2018.04.12"},"doi":"10.1109/DTIS.2018.8368549","language":[{"iso":"eng"}]}