---
res:
  bibo_abstract:
  - In contrast to processors, current reconfigurable devices totally lack programming
    models that would allow for device independent compilation and forward compatibility.
    The key to overcome this limitation is hardware virtualization. In this paper,
    we resort to a macro-pipelined execution model to achieve hardware virtualization
    for data streaming applications. As a hardware implementation we present a hybrid
    multi-context architecture that attaches a coarse-grained reconfigurable array
    to a host CPU. A co-simulation framework enables cycle-accurate simulation of
    the complete architecture. As a case study we map an FIR filter to our virtualized
    hardware model and evaluate different designs. We discuss the impact of the number
    of contexts and the feature of context state on the speedup and the CPU load.@eng
  bibo_authorlist:
  - foaf_Person:
      foaf_givenName: Rolf
      foaf_name: Enzler, Rolf
      foaf_surname: Enzler
  - foaf_Person:
      foaf_givenName: Christian
      foaf_name: Plessl, Christian
      foaf_surname: Plessl
      foaf_workInfoHomepage: http://www.librecat.org/personId=16153
    orcid: 0000-0001-5728-9982
  - foaf_Person:
      foaf_givenName: Marco
      foaf_name: Platzner, Marco
      foaf_surname: Platzner
      foaf_workInfoHomepage: http://www.librecat.org/personId=398
  bibo_doi: 10.1007/b12007
  bibo_volume: 2778
  dct_date: 2003^xs_gYear
  dct_publisher: Springer@
  dct_subject:
  - Zippy
  - multi-context
  - FPGA
  dct_title: Virtualizing Hardware with Multi-Context Reconfigurable Arrays@
...