---
res:
  bibo_abstract:
  - ' Recent generations of high-density and high-speed FPGAs provide a sufficient
    capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid
    CPUs that combine standard CPU cores with reconfigurable coprocessors are an important
    subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded
    on demand while the CPU remains running. However, the lack of high-level design
    tools for partial reconfiguration makes practical implementations a challenging
    task. In this paper, we introduce a design flow to implement hybrid processors
    on Xilinx Virtex. The design flow is based on two techniques, virtual sockets
    and feed-through components, and can efficiently generate partial configurations
    from industry-quality cores. We discuss the design flow and present a fully operational
    audio streaming prototype to demonstrate its feasibility. @eng'
  bibo_authorlist:
  - foaf_Person:
      foaf_givenName: Matthias
      foaf_name: Dyer, Matthias
      foaf_surname: Dyer
  - foaf_Person:
      foaf_givenName: Christian
      foaf_name: Plessl, Christian
      foaf_surname: Plessl
      foaf_workInfoHomepage: http://www.librecat.org/personId=16153
    orcid: 0000-0001-5728-9982
  - foaf_Person:
      foaf_givenName: Marco
      foaf_name: Platzner, Marco
      foaf_surname: Platzner
      foaf_workInfoHomepage: http://www.librecat.org/personId=398
  bibo_doi: 10.1007/3-540-46117-5
  bibo_volume: 2438
  dct_date: 2002^xs_gYear
  dct_publisher: Springer@
  dct_subject:
  - partial reconfiguration
  dct_title: Partially Reconfigurable Cores for Xilinx Virtex@
...