{"date_updated":"2022-01-06T06:56:17Z","type":"mastersthesis","title":"Reconfigurable Accelerators for Minimum Covering","_id":"2430","department":[{"_id":"518"}],"user_id":"24135","citation":{"short":"C. Plessl, Reconfigurable Accelerators for Minimum Covering, Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.","chicago":"Plessl, Christian. <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.","bibtex":"@book{Plessl_2001, title={Reconfigurable Accelerators for Minimum Covering}, publisher={Computer Engineering and Networks Lab, ETH Zurich, Switzerland}, author={Plessl, Christian}, year={2001} }","apa":"Plessl, C. (2001). <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland.","ieee":"C. Plessl, <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.","mla":"Plessl, Christian. <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.","ama":"Plessl C. <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland; 2001."},"date_created":"2018-04-17T15:47:26Z","status":"public","year":"2001","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"}],"abstract":[{"text":"In this report the design and implementation of an instance-specific accelerator for solving minimum covering problems will be presented. After an introduction to configurable computing in general, the minimum covering problem is defined and a branch and bound algorithm to solve it in software is presented. The remainder of the report shows how this branch and bound algorithm can be adopted to hardware. Specifically it is stressed how the various sophisticated strategies for deducing conditions for variables used by software solvers can be adopted to hardware and how a system which uses 3-valued logic to solve this problem can be designed. In addition to these considerations focusing on the architecture of the system, some important details of the actual implementation are given. A prototype has been implemented for showing the feasibility of the concept and for gaining information about speed and size of the hardware implementation. Cycle-accurate simulations for a set of benchmark problems have been done for determining the performance of the accelerator. The speed of the resulting accelerators has been compared to the time a reference software solver (espresso) needs and the resulting speedups have been calculated. I have shown that a raw speedup of several orders of maginitude can be achieved for many problems; for some problems no speedup is achieved yet. After a discussion of the results, ideas for future work are presented.","lang":"eng"}],"publisher":"Computer Engineering and Networks Lab, ETH Zurich, Switzerland"}