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   	<dc:title>Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer</dc:title>
   	<dc:creator>Awny, Ahmed</dc:creator>
   	<dc:creator>Möller, Lothar</dc:creator>
   	<dc:creator>Junio, Josef</dc:creator>
   	<dc:creator>Scheytt, Christoph</dc:creator>
   	<dc:creator>Thiede, Andreas</dc:creator>
   	<dc:description>A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead decision feedback equalizer for 80 Gb/s short-reach optical communication systems is presented. On-wafer tests are developed to determine the maximum operating bit rate of the equalizer. Results are also presented for intersymbol interference mitigation at 80 Gb/s for a 20 GHz bandwidth-limited channel. Further improvements on the architecture of the 80 Gb/s equalizer are discussed and used in the design and on-wafer measurement of a 110 Gb/s equalizer. The equalizers are designed in a 0.13 μm SiGe:C BiCMOS technology. The 80 and 110 Gb/s versions dissipate 4 and 5.75 W, respectively and occupy 2 and 2.56 mm 2 , respectively.</dc:description>
   	<dc:date>2014</dc:date>
   	<dc:type>info:eu-repo/semantics/article</dc:type>
   	<dc:type>doc-type:article</dc:type>
   	<dc:type>text</dc:type>
   	<dc:type>http://purl.org/coar/resource_type/c_6501</dc:type>
   	<dc:identifier>https://ris.uni-paderborn.de/record/24310</dc:identifier>
   	<dc:source>Awny A, Möller L, Junio J, Scheytt C, Thiede A. Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer. &lt;i&gt;IEEE JOURNAL OF SOLID-STATE CIRCUITS&lt;/i&gt;. 2014;Vol.49(No.2):452-470. doi:&lt;a href=&quot;https://doi.org/10.1109/JSSC.2013.2285385&quot;&gt;10.1109/JSSC.2013.2285385&lt;/a&gt;</dc:source>
   	<dc:language>eng</dc:language>
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   	<dc:relation>info:eu-repo/semantics/altIdentifier/issn/1558-173X</dc:relation>
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