[{"department":[{"_id":"58"},{"_id":"51"}],"publication":"IEEE JOURNAL OF SOLID-STATE CIRCUITS","author":[{"first_name":"Ahmed","full_name":"Awny, Ahmed","last_name":"Awny"},{"last_name":"Möller","first_name":"Lothar","full_name":"Möller, Lothar"},{"last_name":"Junio","first_name":"Josef","full_name":"Junio, Josef"},{"last_name":"Scheytt","id":"37144","first_name":"Christoph","full_name":"Scheytt, Christoph","orcid":"https://orcid.org/0000-0002-5950-6618"},{"full_name":"Thiede, Andreas","first_name":"Andreas","id":"538","last_name":"Thiede"}],"date_created":"2021-09-14T07:06:58Z","status":"public","volume":"Vol.49","publication_identifier":{"eissn":["1558-173X"]},"abstract":[{"text":"A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead decision feedback equalizer for 80 Gb/s short-reach optical communication systems is presented. On-wafer tests are developed to determine the maximum operating bit rate of the equalizer. Results are also presented for intersymbol interference mitigation at 80 Gb/s for a 20 GHz bandwidth-limited channel. Further improvements on the architecture of the 80 Gb/s equalizer are discussed and used in the design and on-wafer measurement of a 110 Gb/s equalizer. The equalizers are designed in a 0.13 μm SiGe:C BiCMOS technology. The 80 and 110 Gb/s versions dissipate 4 and 5.75 W, respectively and occupy 2 and 2.56 mm 2 , respectively.","lang":"eng"}],"user_id":"158","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/6648461","relation":"confirmation"}]},"title":"Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer","language":[{"iso":"eng"}],"page":"452-470","year":"2014","citation":{"short":"A. Awny, L. Möller, J. Junio, C. Scheytt, A. Thiede, IEEE JOURNAL OF SOLID-STATE CIRCUITS Vol.49 (2014) 452–470.","ieee":"A. Awny, L. Möller, J. Junio, C. Scheytt, and A. Thiede, “Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. Vol.49, no. No.2, pp. 452–470, 2014, doi: 10.1109/JSSC.2013.2285385.","ama":"Awny A, Möller L, Junio J, Scheytt C, Thiede A. Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer. IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2014;Vol.49(No.2):452-470. doi:10.1109/JSSC.2013.2285385","apa":"Awny, A., Möller, L., Junio, J., Scheytt, C., & Thiede, A. (2014). Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer. IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.49(No.2), 452–470. https://doi.org/10.1109/JSSC.2013.2285385","chicago":"Awny, Ahmed, Lothar Möller, Josef Junio, Christoph Scheytt, and Andreas Thiede. “Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer.” IEEE JOURNAL OF SOLID-STATE CIRCUITS Vol.49, no. No.2 (2014): 452–70. https://doi.org/10.1109/JSSC.2013.2285385.","bibtex":"@article{Awny_Möller_Junio_Scheytt_Thiede_2014, title={Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer}, volume={Vol.49}, DOI={10.1109/JSSC.2013.2285385}, number={No.2}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Awny, Ahmed and Möller, Lothar and Junio, Josef and Scheytt, Christoph and Thiede, Andreas}, year={2014}, pages={452–470} }","mla":"Awny, Ahmed, et al. “Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer.” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. Vol.49, no. No.2, 2014, pp. 452–70, doi:10.1109/JSSC.2013.2285385."},"type":"journal_article","date_updated":"2023-01-25T11:03:36Z","_id":"24310","issue":"No.2","doi":"10.1109/JSSC.2013.2285385"}]