{"publication_status":"published","date_updated":"2022-05-11T16:10:01Z","status":"public","author":[{"first_name":"Somayeh","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"language":[{"iso":"eng"}],"publication_identifier":{"issn":["0923-8174","1573-0727"]},"_id":"29351","year":"2022","type":"journal_article","publication":"Journal of Electronic Testing","title":"Stress-Aware Periodic Test of Interconnects","date_created":"2022-01-14T11:16:34Z","department":[{"_id":"48"}],"keyword":["Electrical and Electronic Engineering"],"publisher":"Springer Science and Business Media LLC","citation":{"mla":"Sadeghi-Kohan, Somayeh, et al. “Stress-Aware Periodic Test of Interconnects.” Journal of Electronic Testing, Springer Science and Business Media LLC, 2022, doi:10.1007/s10836-021-05979-5.","apa":"Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2022). Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. https://doi.org/10.1007/s10836-021-05979-5","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Stress-Aware Periodic Test of Interconnects,” Journal of Electronic Testing, 2022, doi: 10.1007/s10836-021-05979-5.","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Stress-Aware Periodic Test of Interconnects.” Journal of Electronic Testing, 2022. https://doi.org/10.1007/s10836-021-05979-5.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. Published online 2022. doi:10.1007/s10836-021-05979-5","bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, title={Stress-Aware Periodic Test of Interconnects}, DOI={10.1007/s10836-021-05979-5}, journal={Journal of Electronic Testing}, publisher={Springer Science and Business Media LLC}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2022} }"},"user_id":"209","abstract":[{"text":"Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.","lang":"eng"}],"doi":"10.1007/s10836-021-05979-5","article_type":"original"}