{"_id":"35131","type":"conference","doi":"10.1109/fpl53798.2021.00036","publication":"2021 31st International Conference on Field-Programmable Logic and Applications (FPL)","user_id":"3145","author":[{"last_name":"Castells-Rufas","first_name":"David","full_name":"Castells-Rufas, David"},{"last_name":"Marco-Sola","full_name":"Marco-Sola, Santiago","first_name":"Santiago"},{"last_name":"Aguado-Puig","first_name":"Quim","full_name":"Aguado-Puig, Quim"},{"first_name":"Antonio","full_name":"Espinosa-Morales, Antonio","last_name":"Espinosa-Morales"},{"full_name":"Moure, Juan Carlos","first_name":"Juan Carlos","last_name":"Moure"},{"last_name":"Alvarez","full_name":"Alvarez, Lluc","first_name":"Lluc"},{"full_name":"Moreto, Miquel","first_name":"Miquel","last_name":"Moreto"}],"publication_status":"published","citation":{"short":"D. Castells-Rufas, S. Marco-Sola, Q. Aguado-Puig, A. Espinosa-Morales, J.C. Moure, L. Alvarez, M. Moreto, in: 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2021.","bibtex":"@inproceedings{Castells-Rufas_Marco-Sola_Aguado-Puig_Espinosa-Morales_Moure_Alvarez_Moreto_2021, title={OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors}, DOI={<a href=\"https://doi.org/10.1109/fpl53798.2021.00036\">10.1109/fpl53798.2021.00036</a>}, booktitle={2021 31st International Conference on Field-Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Castells-Rufas, David and Marco-Sola, Santiago and Aguado-Puig, Quim and Espinosa-Morales, Antonio and Moure, Juan Carlos and Alvarez, Lluc and Moreto, Miquel}, year={2021} }","chicago":"Castells-Rufas, David, Santiago Marco-Sola, Quim Aguado-Puig, Antonio Espinosa-Morales, Juan Carlos Moure, Lluc Alvarez, and Miquel Moreto. “OpenCL-Based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors.” In <i>2021 31st International Conference on Field-Programmable Logic and Applications (FPL)</i>. IEEE, 2021. <a href=\"https://doi.org/10.1109/fpl53798.2021.00036\">https://doi.org/10.1109/fpl53798.2021.00036</a>.","ieee":"D. Castells-Rufas <i>et al.</i>, “OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors,” 2021, doi: <a href=\"https://doi.org/10.1109/fpl53798.2021.00036\">10.1109/fpl53798.2021.00036</a>.","mla":"Castells-Rufas, David, et al. “OpenCL-Based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors.” <i>2021 31st International Conference on Field-Programmable Logic and Applications (FPL)</i>, IEEE, 2021, doi:<a href=\"https://doi.org/10.1109/fpl53798.2021.00036\">10.1109/fpl53798.2021.00036</a>.","apa":"Castells-Rufas, D., Marco-Sola, S., Aguado-Puig, Q., Espinosa-Morales, A., Moure, J. C., Alvarez, L., &#38; Moreto, M. (2021). OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors. <i>2021 31st International Conference on Field-Programmable Logic and Applications (FPL)</i>. <a href=\"https://doi.org/10.1109/fpl53798.2021.00036\">https://doi.org/10.1109/fpl53798.2021.00036</a>","ama":"Castells-Rufas D, Marco-Sola S, Aguado-Puig Q, et al. OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors. In: <i>2021 31st International Conference on Field-Programmable Logic and Applications (FPL)</i>. IEEE; 2021. doi:<a href=\"https://doi.org/10.1109/fpl53798.2021.00036\">10.1109/fpl53798.2021.00036</a>"},"publisher":"IEEE","date_created":"2023-01-03T10:05:13Z","quality_controlled":"1","status":"public","keyword":["pc2-harp-ressources"],"department":[{"_id":"27"},{"_id":"518"}],"title":"OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors","date_updated":"2023-01-03T10:14:14Z","abstract":[{"lang":"eng","text":"An FPGA accelerator for the computation of the semi-global Levenshtein distance between a pattern and a reference text is presented. The accelerator provides an important benefit to reduce the execution time of read-mappers used in short-read genomic sequencing. Previous attempts to solve the same problem in FPGA use the Myers algorithm following a column approach to compute the dynamic programming table. We use an approach based on diagonals that allows for some resource savings while maintaining a very high throughput of 1 alignment per clock cycle. The design is implemented in OpenCL and tested on two FPGA accelerators. The maximum performance obtained is 91.5 MPairs/s for 100 × 120 sequences and 47 MPairs/s for 300 × 360 sequences, the highest ever reported for this problem."}],"year":"2021","language":[{"iso":"eng"}]}