---
res:
  bibo_abstract:
  - Many heterogeneous embedded systems, for example industrial automation and automotive
    applications, require hard-real time constraints to be exhaustively verified -
    which is a challenging task for the verification engineer. To cope with complexity,
    verification techniques working on different abstraction levels are best practice.
    SystemC is a versatile C++ based design and verification language, offering various
    mechanisms and constructs required for embedded systems modeling. Using the add-on
    SystemC Verification Library (SCV) elemental constrained-random stimuli techniques
    may be used for verification. However, SCV has several drawbacks such as lack
    of functional coverage. In this paper we present a functional coverage library
    that implements parts of the IEEE 1800-2005 SystemVerilog standard and allows
    capturing functional coverage throughout the design and verification process with
    SystemC. Moreover, we will demonstrate the usability of the approach with a case
    study working on a CAN bus model written in SystemC.@eng
  bibo_authorlist:
  - foaf_Person:
      foaf_givenName: Gilles B.
      foaf_name: Defo, Gilles B.
      foaf_surname: Defo
  - foaf_Person:
      foaf_givenName: Wolfgang
      foaf_name: Müller, Wolfgang
      foaf_surname: Müller
      foaf_workInfoHomepage: http://www.librecat.org/personId=16243
  - foaf_Person:
      foaf_givenName: Christoph
      foaf_name: Kuznik, Christoph
      foaf_surname: Kuznik
  bibo_doi: 10.1109/SIES.2010.5551379
  dct_date: 2010^xs_gYear
  dct_language: eng
  dct_publisher: IEEE@
  dct_subject:
  - Libraries
  - Generators
  - Transfer functions
  - Monitoring
  - Computational modeling
  - Driver circuits
  - Adaptation model
  dct_title: Verification of a CAN Bus Model in SystemC with Functional Coverage@
...