{"_id":"45775","status":"public","date_created":"2023-06-26T11:47:42Z","author":[{"last_name":"Luchterhandt","full_name":"Luchterhandt, Lars","first_name":"Lars"},{"first_name":"Tom","last_name":"Nellius","full_name":"Nellius, Tom"},{"first_name":"Robert","last_name":"Beck","full_name":"Beck, Robert"},{"full_name":"Dömer, Rainer","last_name":"Dömer","first_name":"Rainer"},{"full_name":"Kneuper, Pascal","last_name":"Kneuper","id":"47367","first_name":"Pascal"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"full_name":"Sadiye, Babak","last_name":"Sadiye","id":"93634","first_name":"Babak"}],"year":"2023","user_id":"16243","citation":{"ieee":"L. Luchterhandt <i>et al.</i>, “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg, 2023.","bibtex":"@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2023, title={Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture}, booktitle={MBMV 2023 - 26. Workshop \"Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg}, publisher={VDE Verlag}, author={Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}, year={2023} }","ama":"Luchterhandt L, Nellius T, Beck R, et al. Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. In: <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>. VDE Verlag; 2023.","short":"L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B. Sadiye, in: MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg, VDE Verlag, 2023.","apa":"Luchterhandt, L., Nellius, T., Beck, R., Dömer, R., Kneuper, P., Müller, W., &#38; Sadiye, B. (2023). Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>. MBMV 2023, Freiburg, Freiburg.","chicago":"Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” In <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>. VDE Verlag, 2023.","mla":"Luchterhandt, Lars, et al. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>, VDE Verlag, 2023."},"publisher":"VDE Verlag","type":"conference","language":[{"iso":"eng"}],"date_updated":"2024-04-18T20:07:00Z","title":"Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture","publication":"MBMV 2023 - 26. Workshop \"Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg","abstract":[{"text":"RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple\r\nRISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core\r\nprocessors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells\r\n(GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories.\r\nThis paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level\r\n(RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based\r\nimplementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This\r\nwork also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with\r\ndifferent local address spaces.","lang":"eng"}],"related_material":{"link":[{"url":"https://cca.informatik.uni-freiburg.de/mbmv23/slides/luchterhandt.pdf","relation":"slides"},{"url":"https://www.vde-verlag.de/proceedings-de/456065012.html","relation":"software"}]},"conference":{"end_date":"2023.03.24","name":"MBMV 2023, Freiburg","location":"Freiburg","start_date":"2023.03.23"}}