{"year":"2023","_id":"54241","date_updated":"2024-05-15T13:30:54Z","type":"bachelorsthesis","title":"Development of a Power Analysis Framework for Embedded FPGA Accelerators","author":[{"full_name":"Reuter, Lucas David","last_name":"Reuter","first_name":"Lucas David"}],"department":[{"_id":"78"}],"date_created":"2024-05-13T13:56:45Z","status":"public","citation":{"bibtex":"@book{Reuter_2023, title={Development of a Power Analysis Framework for Embedded FPGA Accelerators}, publisher={Paderborn University}, author={Reuter, Lucas David}, year={2023} }","short":"L.D. Reuter, Development of a Power Analysis Framework for Embedded FPGA Accelerators, Paderborn University, 2023.","chicago":"Reuter, Lucas David. <i>Development of a Power Analysis Framework for Embedded FPGA Accelerators</i>. Paderborn University, 2023.","apa":"Reuter, L. D. (2023). <i>Development of a Power Analysis Framework for Embedded FPGA Accelerators</i>. Paderborn University.","mla":"Reuter, Lucas David. <i>Development of a Power Analysis Framework for Embedded FPGA Accelerators</i>. Paderborn University, 2023.","ieee":"L. D. Reuter, <i>Development of a Power Analysis Framework for Embedded FPGA Accelerators</i>. Paderborn University, 2023.","ama":"Reuter LD. <i>Development of a Power Analysis Framework for Embedded FPGA Accelerators</i>. Paderborn University; 2023."},"supervisor":[{"last_name":"Jentzsch","first_name":"Felix","id":"55631","orcid":"0000-0003-4987-5708","full_name":"Jentzsch, Felix"},{"full_name":"Platzner, Marco","id":"398","first_name":"Marco","last_name":"Platzner"}],"user_id":"398","publisher":"Paderborn University","language":[{"iso":"eng"}]}