Development of a Power Analysis Framework for Embedded FPGA Accelerators

thesis Development of a Power Analysis Framework for Embedded FPGA Accelerators Lucas David Reuter author Felix Jentzsch supervisor Marco Platzner supervisor 78 department Computing Resources Provided by the Paderborn Center for Parallel Computing project Paderborn University2023 eng Reuter, Lucas David. Development of a Power Analysis Framework for Embedded FPGA Accelerators. Paderborn University, 2023. L.D. Reuter, Development of a Power Analysis Framework for Embedded FPGA Accelerators, Paderborn University, 2023. L. D. Reuter, Development of a Power Analysis Framework for Embedded FPGA Accelerators. Paderborn University, 2023. Reuter, L. D. (2023). Development of a Power Analysis Framework for Embedded FPGA Accelerators. Paderborn University. @book{Reuter_2023, title={Development of a Power Analysis Framework for Embedded FPGA Accelerators}, publisher={Paderborn University}, author={Reuter, Lucas David}, year={2023} } Reuter LD. Development of a Power Analysis Framework for Embedded FPGA Accelerators. Paderborn University; 2023. Reuter, Lucas David. Development of a Power Analysis Framework for Embedded FPGA Accelerators. Paderborn University, 2023. 542412024-05-13T13:56:45Z2026-04-27T14:21:10Z