{"_id":"56607","title":"HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory","citation":{"bibtex":"@inproceedings{Tareen_Meyer_Plessl_Kenter_2024, title={HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory}, volume={35}, DOI={10.1109/fccm60383.2024.00014}, booktitle={2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Tareen, Abdul Rehman and Meyer, Marius and Plessl, Christian and Kenter, Tobias}, year={2024} }","ieee":"A. R. Tareen, M. Meyer, C. Plessl, and T. Kenter, “HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory,” in 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2024, vol. 35, doi: 10.1109/fccm60383.2024.00014.","mla":"Tareen, Abdul Rehman, et al. “HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory.” 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), vol. 35, IEEE, 2024, doi:10.1109/fccm60383.2024.00014.","ama":"Tareen AR, Meyer M, Plessl C, Kenter T. HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory. In: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). Vol 35. IEEE; 2024. doi:10.1109/fccm60383.2024.00014","apa":"Tareen, A. R., Meyer, M., Plessl, C., & Kenter, T. (2024). HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory. 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 35. https://doi.org/10.1109/fccm60383.2024.00014","chicago":"Tareen, Abdul Rehman, Marius Meyer, Christian Plessl, and Tobias Kenter. “HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory.” In 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Vol. 35. IEEE, 2024. https://doi.org/10.1109/fccm60383.2024.00014.","short":"A.R. Tareen, M. Meyer, C. Plessl, T. Kenter, in: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2024."},"year":"2024","publisher":"IEEE","publication":"2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","user_id":"3145","department":[{"_id":"27"},{"_id":"518"}],"status":"public","author":[{"full_name":"Tareen, Abdul Rehman","last_name":"Tareen","id":"76938","first_name":"Abdul Rehman"},{"last_name":"Meyer","full_name":"Meyer, Marius","id":"40778","first_name":"Marius"},{"id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias","id":"3145"}],"language":[{"iso":"eng"}],"quality_controlled":"1","doi":"10.1109/fccm60383.2024.00014","publication_status":"published","date_created":"2024-10-14T07:59:08Z","date_updated":"2024-10-14T12:27:55Z","intvolume":" 35","volume":35,"type":"conference"}