---
res:
  bibo_abstract:
  - One major obstacle for a wide spread FPGA usage in general-purpose computing is
    the development tool flow that requires much higher effort than for pure software
    solutions. Convey Computer promises a solution to this problem for their HC-1
    platform, where the FPGAs are configured to run as a vector processor and the software
    source code can be annotated with pragmas that guide an automated vectorization
    process. We investigate this approach for a stereo matching algorithm that has
    abundant parallelism and a number of different computational patterns. We note
    that for this case study the automated vectorization in its current state doesn’t
    hold its productivity promise. However, we also show that using the Vector Personality
    can yield a significant speedups compared to CPU implementations in two of three
    investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations,
    but can come with much reduced development effort.@eng
  bibo_authorlist:
  - foaf_Person:
      foaf_givenName: Tobias
      foaf_name: Kenter, Tobias
      foaf_surname: Kenter
      foaf_workInfoHomepage: http://www.librecat.org/personId=3145
  - foaf_Person:
      foaf_givenName: Christian
      foaf_name: Plessl, Christian
      foaf_surname: Plessl
      foaf_workInfoHomepage: http://www.librecat.org/personId=16153
    orcid: 0000-0001-5728-9982
  - foaf_Person:
      foaf_givenName: Henning
      foaf_name: Schmitz, Henning
      foaf_surname: Schmitz
  bibo_doi: 10.1109/ReConFig.2012.6416773
  dct_date: 2012^xs_gYear
  dct_language: eng
  dct_publisher: IEEE@
  dct_title: Pragma based parallelization - Trading hardware efficiency for ease of
    use?@
...