AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference

conference paper AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference published Gerrit Pape author Bjarne Wintermann author 629000009-0000-0856-6250 Linus Jungemann author 676010009-0003-9757-988X Michael Lass author Marius Meyer author Heinrich Riebler author 8961 Christian Plessl author 161530000-0001-5728-9982 27 department The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025) EKI-App: EKI-App: Energieeffiziente Künstliche Intelligenz im Rechenzentrum durch Approximation von tiefen neuronalen Netzen für Field-Programmable Gate Arrays project 2025Kumamoto, Japan eng Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3728179.3728190 G. Pape, B. Wintermann, L. Jungemann, M. Lass, M. Meyer, H. Riebler, C. Plessl, in: Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2025. Pape, Gerrit, Bjarne Wintermann, Linus Jungemann, Michael Lass, Marius Meyer, Heinrich Riebler, and Christian Plessl. “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference.” In Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2025. <a href="https://doi.org/10.1145/3728179.3728190">https://doi.org/10.1145/3728179.3728190</a>. Pape, G., Wintermann, B., Jungemann, L., Lass, M., Meyer, M., Riebler, H., & Plessl, C. (2025). AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference. Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025) , Kumamoto, Japan. <a href="https://doi.org/10.1145/3728179.3728190">https://doi.org/10.1145/3728179.3728190</a> G. Pape et al., “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference,” presented at the The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025) , Kumamoto, Japan, 2025, doi: <a href="https://doi.org/10.1145/3728179.3728190">10.1145/3728179.3728190</a>. Pape G, Wintermann B, Jungemann L, et al. AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference. In: Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ; 2025. doi:<a href="https://doi.org/10.1145/3728179.3728190">10.1145/3728179.3728190</a> @inproceedings{Pape_Wintermann_Jungemann_Lass_Meyer_Riebler_Plessl_2025, title={AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference}, DOI={<a href="https://doi.org/10.1145/3728179.3728190">10.1145/3728179.3728190</a>}, booktitle={Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, author={Pape, Gerrit and Wintermann, Bjarne and Jungemann, Linus and Lass, Michael and Meyer, Marius and Riebler, Heinrich and Plessl, Christian}, year={2025} } Pape, Gerrit, et al. “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference.” Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2025, doi:<a href="https://doi.org/10.1145/3728179.3728190">10.1145/3728179.3728190</a>. 598162025-05-06T09:53:41Z2026-05-13T09:46:42Z