SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators

article SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators submitted Yaman Umuroglu author Christoph Berganski author 98854 Felix Jentzsch author 556310000-0003-4987-5708 Michal Danilowicz author Tomasz Kryjak author Charalampos Bezaitis author Magnus Sjalander author Ian Colbert author Thomas Preusser author Jakoba Petri-Koenig author Michaela Blott author 78 department Computing Resources Provided by the Paderborn Center for Parallel Computing project While neural network quantization effectively reduces the cost of matrix multiplications, aggressive quantization can expose non-matrix-multiply operations as significant performance and resource bottlenecks on embedded systems. Addressing such bottlenecks requires a comprehensive approach to tailoring the precision across operations in the inference computation. To this end, we introduce scaled-integer range analysis (SIRA), a static analysis technique employing interval arithmetic to determine the range, scale, and bias for tensors in quantized neural networks. We show how this information can be exploited to reduce the resource footprint of FPGA dataflow neural network accelerators via tailored bitwidth adaptation for accumulators and downstream operations, aggregation of scales and biases, and conversion of consecutive elementwise operations to thresholding operations. We integrate SIRA-driven optimizations into the open-source FINN framework, then evaluate their effectiveness across a range of quantized neural network workloads and compare implementation alternatives for non-matrix-multiply operations. We demonstrate an average reduction of 17\% for LUTs, 66\% for DSPs, and 22\% for accumulator bitwidths with SIRA optimizations, providing detailed benchmark analysis and analytical models to guide the implementation style for non-matrix layers. Finally, we open-source SIRA to facilitate community exploration of its benefits across various applications and hardware platforms. 2026 eng ACM Transactions on Reconfigurable Technology and Systems 1936-740610.1145/3807510 Umuroglu Y, Berganski C, Jentzsch F, et al. SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators. ACM Transactions on Reconfigurable Technology and Systems. doi:<a href="https://doi.org/10.1145/3807510">10.1145/3807510</a> @article{Umuroglu_Berganski_Jentzsch_Danilowicz_Kryjak_Bezaitis_Sjalander_Colbert_Preusser_Petri-Koenig_et al., title={SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators}, DOI={<a href="https://doi.org/10.1145/3807510">10.1145/3807510</a>}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={Umuroglu, Yaman and Berganski, Christoph and Jentzsch, Felix and Danilowicz, Michal and Kryjak, Tomasz and Bezaitis, Charalampos and Sjalander, Magnus and Colbert, Ian and Preusser, Thomas and Petri-Koenig, Jakoba and et al.} } Umuroglu, Yaman, et al. “SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators.” ACM Transactions on Reconfigurable Technology and Systems, doi:<a href="https://doi.org/10.1145/3807510">10.1145/3807510</a>. Y. Umuroglu, C. Berganski, F. Jentzsch, M. Danilowicz, T. Kryjak, C. Bezaitis, M. Sjalander, I. Colbert, T. Preusser, J. Petri-Koenig, M. Blott, ACM Transactions on Reconfigurable Technology and Systems (n.d.). Umuroglu, Yaman, Christoph Berganski, Felix Jentzsch, Michal Danilowicz, Tomasz Kryjak, Charalampos Bezaitis, Magnus Sjalander, et al. “SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators.” ACM Transactions on Reconfigurable Technology and Systems, n.d. <a href="https://doi.org/10.1145/3807510">https://doi.org/10.1145/3807510</a>. Umuroglu, Y., Berganski, C., Jentzsch, F., Danilowicz, M., Kryjak, T., Bezaitis, C., Sjalander, M., Colbert, I., Preusser, T., Petri-Koenig, J., & Blott, M. (n.d.). SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators. ACM Transactions on Reconfigurable Technology and Systems. <a href="https://doi.org/10.1145/3807510">https://doi.org/10.1145/3807510</a> Y. Umuroglu et al., “SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators,” ACM Transactions on Reconfigurable Technology and Systems, doi: <a href="https://doi.org/10.1145/3807510">10.1145/3807510</a>. 611522025-09-08T14:10:39Z2026-04-27T14:13:50Z