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<titleInfo><title>A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation</title></titleInfo>


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<name type="personal">
  <namePart type="given">Amir Hossein</namePart>
  <namePart type="family">Hadipour</namePart>
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<name type="personal">
  <namePart type="given">Atousa</namePart>
  <namePart type="family">Jafari</namePart>
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<name type="personal">
  <namePart type="given">Muhammad</namePart>
  <namePart type="family">Awais</namePart>
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<name type="personal">
  <namePart type="given">Marco</namePart>
  <namePart type="family">Platzner</namePart>
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  <identifier type="local">78</identifier>
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<originInfo><publisher>IEEE</publisher><dateIssued encoding="w3cdtf">2025</dateIssued>
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<relatedItem type="host"><titleInfo><title>2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</title></titleInfo><identifier type="doi">10.1109/ddecs63720.2025.11006769</identifier>
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<ieee>A. H. Hadipour, A. Jafari, M. Awais, and M. Platzner, “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation,” 2025, doi: &lt;a href=&quot;https://doi.org/10.1109/ddecs63720.2025.11006769&quot;&gt;10.1109/ddecs63720.2025.11006769&lt;/a&gt;.</ieee>
<apa>Hadipour, A. H., Jafari, A., Awais, M., &amp;#38; Platzner, M. (2025). A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation. &lt;i&gt;2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)&lt;/i&gt;. &lt;a href=&quot;https://doi.org/10.1109/ddecs63720.2025.11006769&quot;&gt;https://doi.org/10.1109/ddecs63720.2025.11006769&lt;/a&gt;</apa>
<short>A.H. Hadipour, A. Jafari, M. Awais, M. Platzner, in: 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, 2025.</short>
<chicago>Hadipour, Amir Hossein, Atousa Jafari, Muhammad Awais, and Marco Platzner. “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation.” In &lt;i&gt;2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)&lt;/i&gt;. IEEE, 2025. &lt;a href=&quot;https://doi.org/10.1109/ddecs63720.2025.11006769&quot;&gt;https://doi.org/10.1109/ddecs63720.2025.11006769&lt;/a&gt;.</chicago>
<mla>Hadipour, Amir Hossein, et al. “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation.” &lt;i&gt;2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)&lt;/i&gt;, IEEE, 2025, doi:&lt;a href=&quot;https://doi.org/10.1109/ddecs63720.2025.11006769&quot;&gt;10.1109/ddecs63720.2025.11006769&lt;/a&gt;.</mla>
<bibtex>@inproceedings{Hadipour_Jafari_Awais_Platzner_2025, title={A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation}, DOI={&lt;a href=&quot;https://doi.org/10.1109/ddecs63720.2025.11006769&quot;&gt;10.1109/ddecs63720.2025.11006769&lt;/a&gt;}, booktitle={2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)}, publisher={IEEE}, author={Hadipour, Amir Hossein and Jafari, Atousa and Awais, Muhammad and Platzner, Marco}, year={2025} }</bibtex>
<ama>Hadipour AH, Jafari A, Awais M, Platzner M. A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation. In: &lt;i&gt;2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)&lt;/i&gt;. IEEE; 2025. doi:&lt;a href=&quot;https://doi.org/10.1109/ddecs63720.2025.11006769&quot;&gt;10.1109/ddecs63720.2025.11006769&lt;/a&gt;</ama>
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