{"year":"2025","_id":"62108","title":"A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids","citation":{"ieee":"L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Mueller, and R. Dömer, “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids,” 2025, doi: <a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>.","mla":"Luchterhandt, Lars, et al. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>.","ama":"Luchterhandt L, Govindasamy V, Wang Y, Scheytt C, Mueller W, Dömer R. A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. In: <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. IEEE; 2025. doi:<a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>","bibtex":"@inproceedings{Luchterhandt_Govindasamy_Wang_Scheytt_Mueller_Dömer_2025, title={A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids}, DOI={<a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>}, booktitle={2025 Forum on Specification &#38;amp;amp; Design Languages (FDL)}, publisher={IEEE}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Scheytt, Christoph and Mueller, Wolfgang and Dömer, Rainer}, year={2025} }","short":"L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Mueller, R. Dömer, in: 2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL), IEEE, 2025.","apa":"Luchterhandt, L., Govindasamy, V., Wang, Y., Scheytt, C., Mueller, W., &#38; Dömer, R. (2025). A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. <a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">https://doi.org/10.1109/fdl68117.2025.11165408</a>","chicago":"Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Christoph Scheytt, Wolfgang Mueller, and Rainer Dömer. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” In <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. IEEE, 2025. <a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">https://doi.org/10.1109/fdl68117.2025.11165408</a>."},"publication":"2025 Forum on Specification &amp;amp; Design Languages (FDL)","publisher":"IEEE","user_id":"16243","doi":"10.1109/fdl68117.2025.11165408","publication_status":"published","author":[{"full_name":"Luchterhandt, Lars","last_name":"Luchterhandt","first_name":"Lars"},{"full_name":"Govindasamy, Vivek","last_name":"Govindasamy","first_name":"Vivek"},{"first_name":"Yutong","full_name":"Wang, Yutong","last_name":"Wang"},{"first_name":"Christoph","full_name":"Scheytt, Christoph","last_name":"Scheytt"},{"first_name":"Wolfgang","last_name":"Mueller","full_name":"Mueller, Wolfgang"},{"first_name":"Rainer","last_name":"Dömer","full_name":"Dömer, Rainer"}],"status":"public","department":[{"_id":"58"}],"type":"conference","date_created":"2025-11-06T09:47:40Z","date_updated":"2025-11-06T10:03:47Z"}