---
res:
  bibo_abstract:
  - Resilient systems require monitoring and prediction of environmental and intrinsic
    conditions and the ability to adapt to changing circumstances to optimize the
    trade-off between performance, power consumption, and fault tolerance. TETRISC
    was introduced as a resilient multicore RISC-V processor system based on the PULPissimo
    platform. This paper presents the migration of TETRISC to the Rocket Chip SoC,
    which is freely scalable to the number of processors through parametrizable Chisel
    models. As such, we discuss and evaluate the main advantages and obstacles that
    come with the Chipyard framework for RTL simulation and FPGA synthesis for the
    rapid prototyping of resilient, scalable architectures that are online configurable
    through software for different multicore and lock-step modes.@eng
  bibo_authorlist:
  - foaf_Person:
      foaf_givenName: Kai Arne
      foaf_name: Hannemann, Kai Arne
      foaf_surname: Hannemann
      foaf_workInfoHomepage: http://www.librecat.org/personId=63972
  - foaf_Person:
      foaf_givenName: Lars
      foaf_name: Luchterhandt, Lars
      foaf_surname: Luchterhandt
  - foaf_Person:
      foaf_givenName: Wolfgang
      foaf_name: Müller, Wolfgang
      foaf_surname: Müller
      foaf_workInfoHomepage: http://www.librecat.org/personId=16243
  - foaf_Person:
      foaf_givenName: Markus
      foaf_name: Ulbricht, Markus
      foaf_surname: Ulbricht
  - foaf_Person:
      foaf_givenName: Li
      foaf_name: Lu, Li
      foaf_surname: Lu
  dct_date: 2026^xs_gYear
  dct_language: eng
  dct_subject:
  - RISC-V
  - Multicore
  - Fault Tolerant
  - TETRISC
  - Chisel
  - Chipyard
  dct_title: Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations@
...