---
res:
  bibo_abstract:
  - Resilient systems require monitoring and prediction of environmental and intrinsic
    conditions, as well as the ability to adapt to environmental hazards while optimizing
    the trade-off among performance, power consumption, and fault tolerance. TETRISC
    was introduced as a resilient multicore RISC-V processor system based on the PULPissimo
    platform. We introduce the migration of TETRISC to the open-source Rocket Chip
    SoC, targeting scalable TETRISC Chisel implementations. As such, we discuss and
    evaluate the main advantages and obstacles that come with the Chipyard framework
    for RTL simulation and FPGA synthesis, enabling rapid prototyping of resilient,
    scalable architectures configurable for multicore and lockstep modes.@eng
  bibo_authorlist:
  - foaf_Person:
      foaf_givenName: Kai Arne
      foaf_name: Hannemann, Kai Arne
      foaf_surname: Hannemann
      foaf_workInfoHomepage: http://www.librecat.org/personId=63972
  - foaf_Person:
      foaf_givenName: Lars Markus
      foaf_name: Luchterhandt, Lars Markus
      foaf_surname: Luchterhandt
      foaf_workInfoHomepage: http://www.librecat.org/personId=74648
  - foaf_Person:
      foaf_givenName: Wolfgang
      foaf_name: Müller, Wolfgang
      foaf_surname: Müller
      foaf_workInfoHomepage: http://www.librecat.org/personId=16243
  - foaf_Person:
      foaf_givenName: Markus
      foaf_name: Ulbricht, Markus
      foaf_surname: Ulbricht
  - foaf_Person:
      foaf_givenName: Li
      foaf_name: Lu, Li
      foaf_surname: Lu
  - foaf_Person:
      foaf_givenName: J. Christoph
      foaf_name: Scheytt, J. Christoph
      foaf_surname: Scheytt
      foaf_workInfoHomepage: http://www.librecat.org/personId=37144
    orcid: '0000-0002-5950-6618 '
  dct_date: 2026^xs_gYear
  dct_language: eng
  dct_title: 'TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture@'
...