TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture Hannemann, Kai Arne Luchterhandt, Lars Markus Müller, Wolfgang Ulbricht, Markus Lu, Li Scheytt, J. Christoph Resilient systems require monitoring and prediction of environmental and intrinsic conditions, as well as the ability to adapt to environmental hazards while optimizing the trade-off among performance, power consumption, and fault tolerance. TETRISC was introduced as a resilient multicore RISC-V processor system based on the PULPissimo platform. We introduce the migration of TETRISC to the open-source Rocket Chip SoC, targeting scalable TETRISC Chisel implementations. As such, we discuss and evaluate the main advantages and obstacles that come with the Chipyard framework for RTL simulation and FPGA synthesis, enabling rapid prototyping of resilient, scalable architectures configurable for multicore and lockstep modes. 2026 info:eu-repo/semantics/conferenceObject doc-type:conferenceObject text http://purl.org/coar/resource_type/c_5794 https://ris.uni-paderborn.de/record/65595 Hannemann KA, Luchterhandt LM, Müller W, Ulbricht M, Lu L, Scheytt JC. TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture. In: <i>29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>. ; 2026. eng info:eu-repo/semantics/closedAccess