[{"year":"2023","title":"Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures","status":"public","citation":{"ama":"Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures. Published online 2023. doi:<a href=\"https://doi.org/10.48550/ARXIV.2303.12128\">10.48550/ARXIV.2303.12128</a>","bibtex":"@article{Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures_2023, DOI={<a href=\"https://doi.org/10.48550/ARXIV.2303.12128\">10.48550/ARXIV.2303.12128</a>}, year={2023} }","mla":"<i>Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures</i>. 2023, doi:<a href=\"https://doi.org/10.48550/ARXIV.2303.12128\">10.48550/ARXIV.2303.12128</a>.","chicago":"“Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures,” 2023. <a href=\"https://doi.org/10.48550/ARXIV.2303.12128\">https://doi.org/10.48550/ARXIV.2303.12128</a>.","short":"(2023).","apa":"<i>Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures</i>. (2023). <a href=\"https://doi.org/10.48550/ARXIV.2303.12128\">https://doi.org/10.48550/ARXIV.2303.12128</a>","ieee":"“Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures,” 2023, doi: <a href=\"https://doi.org/10.48550/ARXIV.2303.12128\">10.48550/ARXIV.2303.12128</a>."},"date_updated":"2026-07-05T14:46:35Z","_id":"66198","date_created":"2026-07-03T21:16:49Z","doi":"10.48550/ARXIV.2303.12128","user_id":"128464","type":"journal_article"}]