{"doi":"10.23919/date51398.2021.9473918","user_id":"128464","_id":"66223","publisher":"IEEE","date_updated":"2026-07-05T14:44:20Z","publication_status":"published","title":"Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance","year":"2021","status":"public","author":[{"last_name":"Buschjager","first_name":"Sebastian","full_name":"Buschjager, Sebastian"},{"first_name":"Jian-Jia","last_name":"Chen","full_name":"Chen, Jian-Jia"},{"first_name":"Kuan-Hsun","last_name":"Chen","full_name":"Chen, Kuan-Hsun"},{"last_name":"Gunzel","first_name":"Mario","full_name":"Gunzel, Mario"},{"full_name":"Hakert, Christian","first_name":"Christian","last_name":"Hakert"},{"first_name":"Katharina","last_name":"Morik","full_name":"Morik, Katharina"},{"full_name":"Novkin, Rodion","first_name":"Rodion","last_name":"Novkin"},{"full_name":"Pfahler, Lukas","last_name":"Pfahler","first_name":"Lukas"},{"last_name":"Yayla","first_name":"Mikail","full_name":"Yayla, Mikail"}],"type":"conference","date_created":"2026-07-03T21:21:45Z","publication":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","citation":{"ieee":"S. Buschjager et al., “Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance,” 2021, doi: 10.23919/date51398.2021.9473918.","apa":"Buschjager, S., Chen, J.-J., Chen, K.-H., Gunzel, M., Hakert, C., Morik, K., Novkin, R., Pfahler, L., & Yayla, M. (2021). Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance. 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). https://doi.org/10.23919/date51398.2021.9473918","short":"S. Buschjager, J.-J. Chen, K.-H. Chen, M. Gunzel, C. Hakert, K. Morik, R. Novkin, L. Pfahler, M. Yayla, in: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2021.","chicago":"Buschjager, Sebastian, Jian-Jia Chen, Kuan-Hsun Chen, Mario Gunzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler, and Mikail Yayla. “Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance.” In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2021. https://doi.org/10.23919/date51398.2021.9473918.","mla":"Buschjager, Sebastian, et al. “Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance.” 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2021, doi:10.23919/date51398.2021.9473918.","bibtex":"@inproceedings{Buschjager_Chen_Chen_Gunzel_Hakert_Morik_Novkin_Pfahler_Yayla_2021, title={Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance}, DOI={10.23919/date51398.2021.9473918}, booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={IEEE}, author={Buschjager, Sebastian and Chen, Jian-Jia and Chen, Kuan-Hsun and Gunzel, Mario and Hakert, Christian and Morik, Katharina and Novkin, Rodion and Pfahler, Lukas and Yayla, Mikail}, year={2021} }","ama":"Buschjager S, Chen J-J, Chen K-H, et al. Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance. In: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE; 2021. doi:10.23919/date51398.2021.9473918"}}