[{"user_id":"128464","doi":"10.1109/nvmsa51238.2020.9188172","_id":"66235","publisher":"IEEE","publication_status":"published","date_updated":"2026-07-05T14:44:49Z","year":"2020","title":"NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via NAND-SPIN","status":"public","author":[{"full_name":"Cheng, Wei-Chun","first_name":"Wei-Chun","last_name":"Cheng"},{"full_name":"Chen, Shuo-Han","last_name":"Chen","first_name":"Shuo-Han"},{"full_name":"Chang, Yuan-Hao","last_name":"Chang","first_name":"Yuan-Hao"},{"first_name":"Kuan-Hsun","last_name":"Chen","full_name":"Chen, Kuan-Hsun"},{"full_name":"Chen, Jian-Jia","first_name":"Jian-Jia","last_name":"Chen"},{"first_name":"Tseng-Yi","last_name":"Chen","full_name":"Chen, Tseng-Yi"},{"full_name":"Yang, Ming-Chang","last_name":"Yang","first_name":"Ming-Chang"},{"first_name":"Wei-Kuan","last_name":"Shih","full_name":"Shih, Wei-Kuan"}],"type":"conference","date_created":"2026-07-03T21:24:49Z","publication":"2020 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA)","citation":{"ieee":"W.-C. Cheng <i>et al.</i>, “NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via NAND-SPIN,” 2020, doi: <a href=\"https://doi.org/10.1109/nvmsa51238.2020.9188172\">10.1109/nvmsa51238.2020.9188172</a>.","apa":"Cheng, W.-C., Chen, S.-H., Chang, Y.-H., Chen, K.-H., Chen, J.-J., Chen, T.-Y., Yang, M.-C., &#38; Shih, W.-K. (2020). NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via NAND-SPIN. <i>2020 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA)</i>. <a href=\"https://doi.org/10.1109/nvmsa51238.2020.9188172\">https://doi.org/10.1109/nvmsa51238.2020.9188172</a>","chicago":"Cheng, Wei-Chun, Shuo-Han Chen, Yuan-Hao Chang, Kuan-Hsun Chen, Jian-Jia Chen, Tseng-Yi Chen, Ming-Chang Yang, and Wei-Kuan Shih. “NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-Based FTL via NAND-SPIN.” In <i>2020 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA)</i>. IEEE, 2020. <a href=\"https://doi.org/10.1109/nvmsa51238.2020.9188172\">https://doi.org/10.1109/nvmsa51238.2020.9188172</a>.","short":"W.-C. Cheng, S.-H. Chen, Y.-H. Chang, K.-H. Chen, J.-J. Chen, T.-Y. Chen, M.-C. Yang, W.-K. Shih, in: 2020 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA), IEEE, 2020.","mla":"Cheng, Wei-Chun, et al. “NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-Based FTL via NAND-SPIN.” <i>2020 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA)</i>, IEEE, 2020, doi:<a href=\"https://doi.org/10.1109/nvmsa51238.2020.9188172\">10.1109/nvmsa51238.2020.9188172</a>.","bibtex":"@inproceedings{Cheng_Chen_Chang_Chen_Chen_Chen_Yang_Shih_2020, title={NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via NAND-SPIN}, DOI={<a href=\"https://doi.org/10.1109/nvmsa51238.2020.9188172\">10.1109/nvmsa51238.2020.9188172</a>}, booktitle={2020 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA)}, publisher={IEEE}, author={Cheng, Wei-Chun and Chen, Shuo-Han and Chang, Yuan-Hao and Chen, Kuan-Hsun and Chen, Jian-Jia and Chen, Tseng-Yi and Yang, Ming-Chang and Shih, Wei-Kuan}, year={2020} }","ama":"Cheng W-C, Chen S-H, Chang Y-H, et al. NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via NAND-SPIN. In: <i>2020 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA)</i>. IEEE; 2020. doi:<a href=\"https://doi.org/10.1109/nvmsa51238.2020.9188172\">10.1109/nvmsa51238.2020.9188172</a>"}}]