A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids Luchterhandt, Lars Govindasamy, Vivek Wang, Yutong Scheytt, Christoph Müller, Wolfgang Dömer, Rainer IEEE 2025 info:eu-repo/semantics/conferenceObject doc-type:conferenceObject text http://purl.org/coar/resource_type/c_5794 https://ris.uni-paderborn.de/record/66520 Luchterhandt L, Govindasamy V, Wang Y, Scheytt C, Müller W, Dömer R. A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. In: <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. IEEE; 2025. doi:<a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a> eng info:eu-repo/semantics/altIdentifier/doi/10.1109/fdl68117.2025.11165408 info:eu-repo/semantics/closedAccess