[{"user_id":"16243","doi":"10.1109/fdl68117.2025.11165408","publisher":"IEEE","_id":"66520","language":[{"iso":"eng"}],"publication_status":"published","date_updated":"2026-07-16T15:17:01Z","author":[{"first_name":"Lars","last_name":"Luchterhandt","full_name":"Luchterhandt, Lars","id":"74648"},{"last_name":"Govindasamy","first_name":"Vivek","full_name":"Govindasamy, Vivek"},{"full_name":"Wang, Yutong","first_name":"Yutong","last_name":"Wang"},{"last_name":"Scheytt","first_name":"Christoph","orcid":"0000-0002-5950-6618 ","full_name":"Scheytt, Christoph","id":"37144"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"},{"full_name":"Dömer, Rainer","first_name":"Rainer","last_name":"Dömer"}],"year":"2025","status":"public","title":"A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids","department":[{"_id":"58"}],"type":"conference","date_created":"2026-07-16T15:15:02Z","citation":{"ieee":"L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, and R. Dömer, “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids,” 2025, doi: <a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>.","apa":"Luchterhandt, L., Govindasamy, V., Wang, Y., Scheytt, C., Müller, W., &#38; Dömer, R. (2025). A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. <a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">https://doi.org/10.1109/fdl68117.2025.11165408</a>","short":"L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, R. Dömer, in: 2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL), IEEE, 2025.","chicago":"Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Christoph Scheytt, Wolfgang Müller, and Rainer Dömer. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” In <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. IEEE, 2025. <a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">https://doi.org/10.1109/fdl68117.2025.11165408</a>.","mla":"Luchterhandt, Lars, et al. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>.","bibtex":"@inproceedings{Luchterhandt_Govindasamy_Wang_Scheytt_Müller_Dömer_2025, title={A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids}, DOI={<a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>}, booktitle={2025 Forum on Specification &#38;amp;amp; Design Languages (FDL)}, publisher={IEEE}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Scheytt, Christoph and Müller, Wolfgang and Dömer, Rainer}, year={2025} }","ama":"Luchterhandt L, Govindasamy V, Wang Y, Scheytt C, Müller W, Dömer R. A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. In: <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. IEEE; 2025. doi:<a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>"},"publication":"2025 Forum on Specification &amp;amp; Design Languages (FDL)"}]