conference paper published Lars Luchterhandt author 74648 Vivek Govindasamy author Yutong Wang author Christoph Scheytt author 371440000-0002-5950-6618 Wolfgang Müller author 16243 Rainer Dömer author 58 department IEEE2025 eng 10.1109/fdl68117.2025.11165408 Luchterhandt, Lars, et al. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>, IEEE, 2025, doi:<a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a>. Luchterhandt L, Govindasamy V, Wang Y, Scheytt C, Müller W, Dömer R. A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. In: <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. IEEE; 2025. doi:<a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a> @inproceedings{Luchterhandt_Govindasamy_Wang_Scheytt_Müller_Dömer_2025, title={A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids}, DOI={<a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a>}, booktitle={2025 Forum on Specification &#38;amp;amp; Design Languages (FDL)}, publisher={IEEE}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Scheytt, Christoph and Müller, Wolfgang and Dömer, Rainer}, year={2025} } Luchterhandt, L., Govindasamy, V., Wang, Y., Scheytt, C., Müller, W., &#38; Dömer, R. (2025). A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. <a href="https://doi.org/10.1109/fdl68117.2025.11165408">https://doi.org/10.1109/fdl68117.2025.11165408</a> L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, and R. Dömer, “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids,” 2025, doi: <a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a>. Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Christoph Scheytt, Wolfgang Müller, and Rainer Dömer. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” In <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. IEEE, 2025. <a href="https://doi.org/10.1109/fdl68117.2025.11165408">https://doi.org/10.1109/fdl68117.2025.11165408</a>. L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, R. Dömer, in: 2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL), IEEE, 2025. 665202026-07-16T15:15:02Z2026-07-16T15:17:01Z