---
_id: '66520'
author:
- first_name: Lars
  full_name: Luchterhandt, Lars
  id: '74648'
  last_name: Luchterhandt
- first_name: Vivek
  full_name: Govindasamy, Vivek
  last_name: Govindasamy
- first_name: Yutong
  full_name: Wang, Yutong
  last_name: Wang
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
  orcid: '0000-0002-5950-6618 '
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Rainer
  full_name: Dömer, Rainer
  last_name: Dömer
citation:
  ama: 'Luchterhandt L, Govindasamy V, Wang Y, Scheytt C, Müller W, Dömer R. A Quantitative
    Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor
    Grids. In: <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>.
    IEEE; 2025. doi:<a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a>'
  apa: Luchterhandt, L., Govindasamy, V., Wang, Y., Scheytt, C., Müller, W., &#38;
    Dömer, R. (2025). A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in
    System Level Design of RISC-V Processor Grids. <i>2025 Forum on Specification
    &#38;amp;Amp; Design Languages (FDL)</i>. <a href="https://doi.org/10.1109/fdl68117.2025.11165408">https://doi.org/10.1109/fdl68117.2025.11165408</a>
  bibtex: '@inproceedings{Luchterhandt_Govindasamy_Wang_Scheytt_Müller_Dömer_2025,
    title={A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level
    Design of RISC-V Processor Grids}, DOI={<a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a>},
    booktitle={2025 Forum on Specification &#38;amp;amp; Design Languages (FDL)},
    publisher={IEEE}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang,
    Yutong and Scheytt, Christoph and Müller, Wolfgang and Dömer, Rainer}, year={2025}
    }'
  chicago: Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Christoph Scheytt,
    Wolfgang Müller, and Rainer Dömer. “A Quantitative Guide to Navigate Speed/Accuracy
    Tradeoffs in System Level Design of RISC-V Processor Grids.” In <i>2025 Forum
    on Specification &#38;amp;Amp; Design Languages (FDL)</i>. IEEE, 2025. <a href="https://doi.org/10.1109/fdl68117.2025.11165408">https://doi.org/10.1109/fdl68117.2025.11165408</a>.
  ieee: 'L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, and R. Dömer,
    “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design
    of RISC-V Processor Grids,” 2025, doi: <a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a>.'
  mla: Luchterhandt, Lars, et al. “A Quantitative Guide to Navigate Speed/Accuracy
    Tradeoffs in System Level Design of RISC-V Processor Grids.” <i>2025 Forum on
    Specification &#38;amp;Amp; Design Languages (FDL)</i>, IEEE, 2025, doi:<a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a>.
  short: 'L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, R. Dömer,
    in: 2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL), IEEE, 2025.'
date_created: 2026-07-16T15:15:02Z
date_updated: 2026-07-16T15:17:01Z
department:
- _id: '58'
doi: 10.1109/fdl68117.2025.11165408
language:
- iso: eng
publication: 2025 Forum on Specification &amp;amp; Design Languages (FDL)
publication_status: published
publisher: IEEE
status: public
title: A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design
  of RISC-V Processor Grids
type: conference
user_id: '16243'
year: '2025'
...