---
res:
  bibo_abstract:
  - Massively parallel computer architectures based on identical microprocessor tiles
    are well known for their high scalability and performance. In this work, we introduce
    the design and simulation of a scalable on-chip grid of RISC-V processors with
    local memories in a structured EDA flow. We specify a Grid of Processing Cells
    (GPC) with two non-trivial software applications and successively generate and
    validate the hardware models at lower abstraction levels, namely TLM, ISS, RTL,
    and FPGA. Our comprehensive experimental evaluation of a physical implementation
    on an FPGA shows the true scalability of the GPC architecture. While existing
    works have indicated performance benefits for GPCs at high abstraction levels,
    our results confirm their highly reduced interconnect contention for the first
    time on fully constructed hardware with clock-cycle accuracy at RTL and on FPGAs.@eng
  bibo_authorlist:
  - foaf_Person:
      foaf_givenName: Lars
      foaf_name: Luchterhandt, Lars
      foaf_surname: Luchterhandt
      foaf_workInfoHomepage: http://www.librecat.org/personId=74648
  - foaf_Person:
      foaf_givenName: Vivek
      foaf_name: Govindasamy, Vivek
      foaf_surname: Govindasamy
  - foaf_Person:
      foaf_givenName: Yutong
      foaf_name: Wang, Yutong
      foaf_surname: Wang
  - foaf_Person:
      foaf_givenName: Rainer
      foaf_name: Dömer, Rainer
      foaf_surname: Dömer
  - foaf_Person:
      foaf_givenName: Wolfgang
      foaf_name: Müller, Wolfgang
      foaf_surname: Müller
      foaf_workInfoHomepage: http://www.librecat.org/personId=16243
  - foaf_Person:
      foaf_givenName: Christoph
      foaf_name: Scheytt, Christoph
      foaf_surname: Scheytt
      foaf_workInfoHomepage: http://www.librecat.org/personId=37144
    orcid: '0000-0002-5950-6618 '
  dct_date: 2026^xs_gYear
  dct_language: eng
  dct_publisher: VDE Verlag@
  dct_title: Truly Scalable Grids of RISC-V Processors with Local Memories@
...