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12543 Publications


1995 | Conference Paper | LibreCat-ID: 8267
Corradini A, Heckel R. A Compositional Approach to Structuring and Refinement of Typed Graph Grammars. In: Proceedings of the Joint COMPUGRAPH/SEMAGRAPH Workshop on Graph Rewriting and Computation (SEGRAGRA 1995), Volterra (Italy). Vol 2. Electronic Notes in Theoretical Computer Science . Elsevier; 1995:46-55.
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1995 | Journal Article | LibreCat-ID: 16542
Dellnitz M, Melbourne I. A note on the shadowing lemma and symmetric periodic points. Nonlinearity. 1995:1067-1075. doi:10.1088/0951-7715/8/6/010
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1995 | Conference Paper | LibreCat-ID: 17482
Czumaj A, Meyer auf der Heide F, Stemann V. Simulating shared memory in real time: On the computation power of reconfigurable meshes. In: Proceedings of the 2nd IEEE Workshop on Reconfigurable Architectures. ; 1995:46--59.
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1995 | Journal Article | LibreCat-ID: 16566
Breslauer D, Czumaj A, Dubhashi DP, Meyer auf der Heide F. Transforming comparison model lower bounds to the parallel-random-access-machine. Information Processing Letters. 1995:103-110. doi:10.1016/s0020-0190(97)00032-x
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1995 | Book Chapter | LibreCat-ID: 19414
Eke NO. Zeit/Räume – Aspekte der Zeiterfahrung bei Heiner Müller. In: Buck T, Valentin J-M, Kenfgens N, Vogel D, eds. Heiner Müller – Rückblicke, Perspektiven. Vorträge des Pariser Kolloquiums 1993. Frankfurt a. M.: Lang; 1995:131-152.
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1995 | Dissertation | LibreCat-ID: 19630
Wachsmann A. Eine Bibliothek von Basisdiensten Für Parallelrechner: Routing, Synchronisation, Gemeinsamer Speicher. Universität Paderborn; 1995.
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1995 | Dissertation | LibreCat-ID: 19623
Stemann V. Contention Resolution in Hashing Based Shared Memory Simulations. Universität Paderborn; 1995.
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1995 | Conference Paper | LibreCat-ID: 2187
Meyer auf der Heide F, Scheideler C. Routing with Bounded Buffers and Hot-Potato Routing in Vertex-Symmetric Networks. In: ESA. Lecture Notes in Computer Science. ; 1995:341--354. doi:10.1007/3-540-60313-1_154
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1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. In: {European Design and Test Conference (EDAC/ETC/EUROASIC)}. Paris, France: {IEEE (Comput. Soc. Press)}; 1994:580-585. doi:10.1109/edtc.1994.326815
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1994 | Report | LibreCat-ID: 13025
Hellebrand S, Juergensen A, Stroele A, Wunderlich H-J. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany; 1994.
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