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282 Publications
2014 | Conference Paper | LibreCat-ID: 25120
Mischkalla, F., & Müller, W. (2014). Architectural Low-Power Design Using Transaction-Based System Simulation. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).
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2014 | Conference Paper | LibreCat-ID: 25146
Joy, M. tech. M. M., Müller, W., & Rammig, F.-J. (2014). Source code annotated memory leak detection for soft real time embedded systems with resource constraints. 12th IEEE International Conference on Embedded Computing.
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2014 | Conference Paper | LibreCat-ID: 25144
Mischkalla, F., & Müller, W. (2014). Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation. PATMOS 2014.
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2014 | Conference Paper | LibreCat-ID: 36918
Becker, M., Kuznik, C., & Müller, W. (2014). Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems. ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin. https://doi.org/10.1109/ICCPS.2014.6843726
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| DOI
2014 | Conference Paper | LibreCat-ID: 36917
Kuznik, C., Müller, W., & Defo, G. B. (2014). An Assisted Single Source Verification Metric Model Code Generation Methodology. Proceedings of the Electronic System Level Synthesis Conference (ESLSyn).
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2014 | Conference Paper | LibreCat-ID: 25166
Kuznik, C., & Müller, W. (2014). Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM. 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen.
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2014 | Conference Paper | LibreCat-ID: 25163
Kuznik, C., Defo, B. G., & Müller, W. (2014). Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung. 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) .
LibreCat
2014 | Journal Article | LibreCat-ID: 25151
Kuznik, C., Defo, B. G., & Müller, W. (2014). An Assisted Single Source Verification Metric Model Code Generation Methodology. Electronic System Level Synthesis Conference (ESLSyn).
LibreCat
2014 | Conference Paper | LibreCat-ID: 34585
Koppelmann, B., Messidat, B., Becker, M., Müller, W., & Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. Proceedings of the Design and Verification Conference Europe (DVCON Europe).
LibreCat
2014 | Conference Paper | LibreCat-ID: 34583
Koppelmann, B., Messidat, B., Kuznik, C., Müller, W., Becker, M., & Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. Proceedings of the Design and Verification Conference Europe (DVCON Europe).
LibreCat
2014 | Conference Paper | LibreCat-ID: 34580
Becker, M., Kuznik, C., Müller, W., Koppelmann, B., & Messidat, B. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. Proceedings of the Design and Verification Conference Europe . DVCON Europe.
LibreCat
2014 | Journal Article | LibreCat-ID: 25117
Koppelmann, B., Messidat, B., Becker, M., Kuznik, C., Müller, W., & Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. Design and Verification Conference (DVCON EUROPE).
LibreCat
2014 | Journal Article | LibreCat-ID: 25162
Kuznik, C., & Müller, W. (2014). Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure. Design, Automation and Test in Europe DATE, University Booth, Dresden .
LibreCat
2014 | Conference Paper | LibreCat-ID: 25169
Oetjens, J.-H., Becker, M., Kuznik, C., & Müller, W. (2014). Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. Design Automation Conference (DAC).
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2013 | Conference Paper | LibreCat-ID: 25270
Joy, M. tech. M. M., Müller, W., & Rammig, F.-J. (2013). Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model. Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25271
He, D., & Müller, W. (2013). AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS. Proceedings of International Conference on Applied Computing (AC).
LibreCat
2013 | Conference Paper | LibreCat-ID: 25284
Mischkalla, F., & Müller, W. (2013). Efficient Power Intent Validation Using Loosely-Timed Simulation Models. 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013.
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2013 | Conference Paper | LibreCat-ID: 25291
Becker, M., Kiffmeier, U., & Müller, W. (2013). HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures. 16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25606
Kuznik, C., F. S. Oliveira, M., & Müller, W. (2013). SystemC Verification Components - An enhanced OVM/UVM for SystemC. EdaWorkshop 13.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25612
Mischkalla, F., & Müller, W. (2013). Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen. Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV).
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