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165 Publications
1998 | Misc | LibreCat-ID: 13091
Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.
LibreCat
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.
1998 | Misc | LibreCat-ID: 13092
Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 10th GI/ITG/GMM/IEEE Workshop, 1998.
LibreCat
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 10th GI/ITG/GMM/IEEE Workshop, 1998.
1998 | Book Chapter | LibreCat-ID: 13060
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: Mixed-Mode BIST Using Embedded Processors, Kluwer Academic Publishers, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998, 1998.
LibreCat
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: Mixed-Mode BIST Using Embedded Processors, Kluwer Academic Publishers, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998, 1998.
1998 | Journal Article | LibreCat-ID: 13061
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, Journal of Electronic Testing Theory and Applications - JETTA 12 (1998) 127–138.
LibreCat
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, Journal of Electronic Testing Theory and Applications - JETTA 12 (1998) 127–138.
1998 | Journal Article | LibreCat-ID: 13064
Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
S. Hellebrand, A. Hertwig, H.-J. Wunderlich, IEEE Design and Test 15 (1998) 36–41.
LibreCat
S. Hellebrand, A. Hertwig, H.-J. Wunderlich, IEEE Design and Test 15 (1998) 36–41.
1998 | Conference Paper | LibreCat-ID: 13007
Fast Self-Recovering Controllers
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, in: 16th IEEE VLSI Test Symposium (VTS’98), IEEE, Monterey, CA, USA, 1998, pp. 296–302.
LibreCat
| DOI
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, in: 16th IEEE VLSI Test Symposium (VTS’98), IEEE, Monterey, CA, USA, 1998, pp. 296–302.
1998 | Conference Paper | LibreCat-ID: 13008
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: Design Automation and Test in Europe (DATE’98), Paris, France, 1998, pp. 173–179.
LibreCat
| DOI
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: Design Automation and Test in Europe (DATE’98), Paris, France, 1998, pp. 173–179.
1998 | Conference Paper | LibreCat-ID: 13063
New Transparent RAM BIST Based on Self-Adjusting Output Data Compression
V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, H.-J. Wunderlich, in: Design & Diagnostics of Electronic Circuits & Systems (DDECS’98), Szczyrk, Poland, 1998, pp. 27–33.
LibreCat
V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, H.-J. Wunderlich, in: Design & Diagnostics of Electronic Circuits & Systems (DDECS’98), Szczyrk, Poland, 1998, pp. 27–33.
1997 | Misc | LibreCat-ID: 13089
STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, J. Rajski, M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation, 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.
LibreCat
K.-H. Tsai, S. Hellebrand, J. Rajski, M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation, 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.
1997 | Misc | LibreCat-ID: 13090
Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications, 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
LibreCat
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications, 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.