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165 Publications
2019 | Conference Paper | LibreCat-ID: 12918
M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for Adaptive X-Handling,” in 50th IEEE International Test Conference (ITC), Washington, DC, USA, 2019, pp. 1–8.
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2018 | Misc | LibreCat-ID: 4576
A. Sprenger and S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.
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2018 | Journal Article | LibreCat-ID: 13057
M. Kampmann and S. Hellebrand, “Design For Small Delay Test - A Simulation Study,” Microelectronics Reliability, vol. 80, pp. 124–133, 2018.
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2018 | Misc | LibreCat-ID: 13072
M. Kampmann and S. Hellebrand, Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018.
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2018 | Conference Paper | LibreCat-ID: 29460
R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, and Z. Navabi, “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture,” 2018, doi: 10.1145/3194554.3194599.
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2018 | Conference Paper | LibreCat-ID: 4575
A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test,” 2018, doi: 10.1109/ddecs.2018.00020.
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2018 | Conference Paper | LibreCat-ID: 10575
C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, and H.-J. Wunderlich, “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention,” 2018, doi: 10.1109/ats.2018.00028.
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2018 | Conference Paper | LibreCat-ID: 29459
S. Sadeghi-Kohan, A. Vafaei, and Z. Navabi, “Near-Optimal Node Selection Procedure for Aging Monitor Placement,” 2018, doi: 10.1109/iolts.2018.8474120.
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2017 | Misc | LibreCat-ID: 13078
M. Kampmann and S. Hellebrand, X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz. 29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
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2017 | Conference Paper | LibreCat-ID: 10576
M. Kampmann and S. Hellebrand, “Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test,” 2017, doi: 10.1109/ddecs.2017.7934564.
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2017 | Journal Article | LibreCat-ID: 29462
S. Sadeghi-Kohan, M. Kamal, and Z. Navabi, “Self-Adjusting Monitor for Measuring Aging Rate and Advancement,” IEEE Transactions on Emerging Topics in Computing, vol. 8, no. 3, pp. 627–641, 2017, doi: 10.1109/tetc.2017.2771441.
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2017 | Conference Paper | LibreCat-ID: 29463
M. Jenihhin, A. Kamkin, Z. Navabi, and S. Sadeghi-Kohan, “Universal mitigation of NBTI-induced aging by design randomization,” 2017, doi: 10.1109/ewdts.2016.7807635.
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2015 | Journal Article | LibreCat-ID: 13056
Z. Huang, H. Liang, and S. Hellebrand, “A High Performance SEU Tolerant Latch,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 31, no. 4, pp. 349–359, 2015.
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2015 | Misc | LibreCat-ID: 13077
S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, and H.-J. Wunderlich, Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
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2015 | Conference Paper | LibreCat-ID: 29465
S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, and Z. Navabi, “Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation,” 2015, doi: 10.1109/dtis.2015.7127373.
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2015 | Conference Paper | LibreCat-ID: 29466
S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, and Z. Navabi, “Online self adjusting progressive age monitoring of timing variations,” 2015, doi: 10.1109/dtis.2015.7127368.
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2014 | Journal Article | LibreCat-ID: 13054
S. Hellebrand and H.-J. Wunderlich, “SAT-Based ATPG beyond Stuck-at Fault Testing,” DeGruyter Journal on Information Technology (it), vol. 56, no. 4, pp. 165–172, 2014.
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2014 | Journal Article | LibreCat-ID: 13055
L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, and H.-J. Wunderlich, “Adaptive Bayesian Diagnosis of Intermittent Faults,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 30, no. 5, pp. 527–540, 2014.
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2014 | Journal Article | LibreCat-ID: 46266
B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs,” IEEE Transactions on Computers, pp. 1–1, 2014, doi: 10.1109/tc.2014.2329687.
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2014 | Conference Paper | LibreCat-ID: 46268
M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, and Z. Navabi, “An off-line MDSI interconnect BIST incorporated in BS 1149.1,” 2014, doi: 10.1109/ets.2014.6847847.
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2014 | Conference Paper | LibreCat-ID: 46267
S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, and Z. Navabi, “Improving polynomial datapath debugging with HEDs,” 2014, doi: 10.1109/ets.2014.6847797.
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2013 | Misc | LibreCat-ID: 13075
A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina, 2013.
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2013 | Conference Paper | LibreCat-ID: 46271
S. Sadeghi-Kohan, M. Namaki-Shoushtari, F. Javaheri, and Z. Navabi, “BS 1149.1 extensions for an online interconnect fault detection and recovery,” 2013, doi: 10.1109/test.2012.6401583.
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2013 | Conference Paper | LibreCat-ID: 46270
S. Sadeghi-Kohan, S. Keshavarz, F. Zokaee, F. Farahmandi, and Z. Navabi, “A new structure for interconnect offline testing,” 2013, doi: 10.1109/ewdts.2013.6673207.
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2012 | Misc | LibreCat-ID: 13074
A. Cook, S. Hellebrand, and H.-J. Wunderlich, Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany, 2012.
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2011 | Conference Paper | LibreCat-ID: 13053
A. Cook, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, “Robuster Selbsttest mit Diagnose,” in 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf,” 2011, pp. 48–53.
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2011 | Journal Article | LibreCat-ID: 13052
F. Hopsch et al., “Variation-Aware Fault Modeling,” SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer, vol. 54, no. 4, pp. 1813–1826, 2011.
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2011 | Conference Paper | LibreCat-ID: 46272
A. Kamran, N. Nemati, S. Sadeghi-Kohan, and Z. Navabi, “Virtual tester development using HDL/PLI,” 2011, doi: 10.1109/ewdts.2010.5742156.
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2010 | Misc | LibreCat-ID: 10670
V. Fröse, R. Ibers, and S. Hellebrand, Testdatenkompression mit Hilfe der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
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2010 | Conference Paper | LibreCat-ID: 12987
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” in 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), 2010.
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2010 | Conference Paper | LibreCat-ID: 13051
M. Hunger and S. Hellebrand, “Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 81–88.
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2010 | Misc | LibreCat-ID: 13073
S. Hellebrand, Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180, 2010.
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2010 | Conference Paper | LibreCat-ID: 12983
F. Hopsch et al., “Variation-Aware Fault Modeling,” in 19th IEEE Asian Test Symposium (ATS’10), 2010, pp. 87–93, doi: 10.1109/ats.2010.24.
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2010 | Conference Paper | LibreCat-ID: 12985
T. Indlekofer, M. Schnittger, and S. Hellebrand, “Efficient Test Response Compaction for Robust BIST Using Parity Sequences,” in 28th IEEE International Conference on Computer Design (ICCD’10), 2010, pp. 480–485, doi: 10.1109/iccd.2010.5647648.
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2010 | Conference Paper | LibreCat-ID: 12986
M. Hunger and S. Hellebrand, “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems,” in 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 2010, pp. 101–108, doi: 10.1109/dft.2010.19.
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2010 | Conference Paper | LibreCat-ID: 12988
V. Froese, R. Ibers, and S. Hellebrand, “Reusing NoC-Infrastructure for Test Data Compression,” in 28th IEEE VLSI Test Symposium (VTS’10), 2010, pp. 227–231, doi: 10.1109/vts.2010.5469570.
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2010 | Conference Paper | LibreCat-ID: 13049
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” 2010.
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2010 | Conference Paper | LibreCat-ID: 13050
T. Indlekofer, M. Schnittger, and S. Hellebrand, “Robuster Selbsttest mit extremer Kompaktierung,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 17–24.
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2009 | Conference Paper | LibreCat-ID: 12991
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,” 2009, doi: 10.1109/iolts.2009.5196027.
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2009 | Conference Paper | LibreCat-ID: 12990
S. Hellebrand and M. Hunger, “Are Robust Circuits Really Robust?,” in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 2009, p. 77, doi: 10.1109/dft.2009.28.
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2009 | Conference Paper | LibreCat-ID: 13030
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung,” 2009.
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2008 | Misc | LibreCat-ID: 13033
T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, and C. G. Zoellin, Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008.
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2008 | Misc | LibreCat-ID: 13035
U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008.
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2008 | Conference Paper | LibreCat-ID: 12992
P. Oehler, A. Bosio, G. di Natale, and S. Hellebrand, “A Modular Memory BIST for Optimized Memory Repair,” 2008, doi: 10.1109/iolts.2008.30.
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2008 | Conference Paper | LibreCat-ID: 12994
U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, “Signature Rollback - A Technique for Testing Robust Circuits,” in 26th IEEE VLSI Test Symposium (VTS’08), 2008, pp. 125–130, doi: 10.1109/vts.2008.34.
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2008 | Conference Paper | LibreCat-ID: 12993
M. Hunger and S. Hellebrand, “Verification and Analysis of Self-Checking Properties through ATPG,” 2008, doi: 10.1109/iolts.2008.32.
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2008 | Conference Paper | LibreCat-ID: 13031
M. Hunger and S. Hellebrand, “Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG,” 2008.
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2008 | Conference Paper | LibreCat-ID: 13032
P. Oehler, A. Bosio, G. Di Natale, and S. Hellebrand, “Modularer Selbsttest und optimierte Reparaturanalyse,” 2008.
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2007 | Misc | LibreCat-ID: 13038
S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk), 2007.
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2007 | Misc | LibreCat-ID: 13039
M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.
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2007 | Misc | LibreCat-ID: 13042
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
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2007 | Misc | LibreCat-ID: 13043
S. Hellebrand, Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
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2007 | Conference Paper | LibreCat-ID: 12995
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction,” in 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 2007, pp. 50–58, doi: 10.1109/dft.2007.43.
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2007 | Conference Paper | LibreCat-ID: 12996
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair,” in 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 2007, pp. 185–190, doi: 10.1109/ddecs.2007.4295278.
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2007 | Conference Paper | LibreCat-ID: 12997
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy,” in 12th IEEE European Test Symposium (ETS’07), 2007, pp. 91–96, doi: 10.1109/ets.2007.10.
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2007 | Conference Paper | LibreCat-ID: 13037
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” 2007.
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2007 | Journal Article | LibreCat-ID: 13036
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” Informacije MIDEM, Ljubljana (Invited Paper), vol. 37, no. 4 (124), pp. 212–219, 2007.
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2007 | Journal Article | LibreCat-ID: 13044
M. Ali, S. Hessler, M. Welzl, and S. Hellebrand, “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip,” International Journal on High Performance Systems Architecture, vol. 1, no. 2, pp. 113–123, 2007.
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2007 | Conference Paper | LibreCat-ID: 13040
M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip,” in 4th International Conference on Information Technology: New Generations (ITNG’07), 2007, pp. 1027–1032.
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2007 | Conference Paper | LibreCat-ID: 13041
B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “Test und Zuverlässigkeit nanoelektronischer Systeme,” 2007.
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2006 | Journal Article | LibreCat-ID: 13045
B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme,” it - Information Technology, vol. 48, no. 5, pp. 305–311, 2006.
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2005 | Misc | LibreCat-ID: 13046
P. Oehler and S. Hellebrand, A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany, 2005.
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2005 | Misc | LibreCat-ID: 13101
M. Ali, M. Welzl, and S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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2005 | Misc | LibreCat-ID: 13102
P. Oehler and S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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2005 | Conference Paper | LibreCat-ID: 12999
M. Ali, M. Welzl, M. Zwicknagl, and S. Hellebrand, “Considerations for Fault-Tolerant Networks on Chips,” 2005, doi: 10.1109/icm.2005.1590063.
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2005 | Conference Paper | LibreCat-ID: 13000
P. Oehler and S. Hellebrand, “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities,” in 10th IEEE European Test Symposium (ETS’05), 2005, pp. 148–153, doi: 10.1109/ets.2005.28.
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2005 | Conference Paper | LibreCat-ID: 12998
M. Ali, M. Welzl, and S. Hellebrand, “A Dynamic Routing Mechanism for Network on Chip,” in 23rd IEEE NORCHIP Conference, 2005, pp. 70–73, doi: 10.1109/norchp.2005.1596991.
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2004 | Conference Paper | LibreCat-ID: 13071
M. Liu Jing et al., “Sensor Networks with More Features Using Less Hardware,” in {GOR/NGB Conference Tilburg 2004}, 2004.
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2004 | Misc | LibreCat-ID: 13099
R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, and O. Scherzer, Im Westen viel Neues - Informatik an der Universität Innsbruck. OCG Journal, pp. 28-29, 2004.
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2004 | Misc | LibreCat-ID: 13100
S. Hellebrand, A. Wuertenberger, and C. S. Tautermann, Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France, 2004.
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2004 | Conference Paper | LibreCat-ID: 13001
A. Wuertenberger, C. S. Tautermann, and S. Hellebrand, “Data Compression for Multiple Scan Chains Using Dictionaries with Corrections,” in IEEE International Test Conference (ITC’04), 2004, pp. 926–935, doi: 10.1109/test.2004.1387357.
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2003 | Misc | LibreCat-ID: 13098
R. Breu, S. Hellebrand, and M. Welzl, Experiences from Teaching Software Development in a Java Environment. Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia, 2003.
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2003 | Conference Paper | LibreCat-ID: 13002
A. Wuertenberger, C. S. Tautermann, and S. Hellebrand, “A Hybrid Coding Strategy for Optimized Test Data Compression,” in IEEE International Test Conference (ITC’03), 2003, pp. 451–459, doi: 10.1109/test.2003.1270870.
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2002 | Misc | LibreCat-ID: 13097
S. Hellebrand and A. Wuertenberger, Alternating Run-Length Coding: A Technique for Improved Test Data Compression. IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA, 2002.
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2002 | Journal Article | LibreCat-ID: 13003
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, and V. N. Yarmolik, “Efficient Online and Offline Testing of Embedded DRAMs,” IEEE Transactions on Computers, vol. 51, no. 7, pp. 801–809, 2002, doi: 10.1109/tc.2002.1017700.
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2002 | Journal Article | LibreCat-ID: 13069
S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 18, no. 2, pp. 157–168, 2002.
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2002 | Journal Article | LibreCat-ID: 13070
H. Liang, S. Hellebrand, and H.-J. Wunderlich, “A Mixed-Mode BIST Scheme Based on Folding Compression,” Journal on Computer Science and Technology, vol. 17, no. 2, pp. 203–212, 2002.
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2001 | Misc | LibreCat-ID: 13096
H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE European Test Workshop, Stockholm, Sweden, 2001.
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2001 | Conference Paper | LibreCat-ID: 13004
H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST,” in IEEE International Test Conference (ITC’01), 2001, pp. 894–902, doi: 10.1109/test.2001.966712.
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2001 | Journal Article | LibreCat-ID: 13047
H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, “Deterministic BIST Scheme Based on Reseeding of Folding Counters,” Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan), vol. 38, no. 8, p. 931, 2001.
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2001 | Journal Article | LibreCat-ID: 13068
S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 17, no. 3/4, pp. 341–349, 2001.
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2000 | Misc | LibreCat-ID: 13094
S. Hellebrand and H.-J. Wunderlich, Hardwarepraktikum im Diplomstudiengang Informatik. Handbuch Lehre, Berlin, Raabe Verlag, 2000.
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2000 | Misc | LibreCat-ID: 13095
S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE European Test Workshop, Cascais, Portugal, 2000.
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2000 | Conference Paper | LibreCat-ID: 13005
S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,” in IEEE International Test Conference (ITC’00), 2000, pp. 778–784, doi: 10.1109/test.2000.894274.
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1999 | Book | LibreCat-ID: 13065
S. Hellebrand, Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren. Verlag Dr. Kovac, Hamburg: Verlag Dr. Kovac, Hamburg, 1999.
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1999 | Misc | LibreCat-ID: 13093
S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, Exploiting Symmetries to Speed Up Transparent BIST. 11th GI/ITG/GMM/IEEE Workshop, 1999.
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1999 | Conference Paper | LibreCat-ID: 13006
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, and V. N. Yarmolik, “Error Detecting Refreshment for Embedded DRAMs,” in 17th IEEE VLSI Test Symposium (VTS’99), 1999, pp. 384–390, doi: 10.1109/vtest.1999.766693.
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1999 | Conference Paper | LibreCat-ID: 13066
V. N. Yarmolik, I. V. Bykov, S. Hellebrand, and H.-J. Wunderlich, “Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms,” 1999.
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1999 | Conference Paper | LibreCat-ID: 13067
S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Symmetric Transparent BIST for RAMs,” in Design Automation and Test in Europe (DATE’99), 1999, pp. 702–707.
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1998 | Report | LibreCat-ID: 13029
S. Hellebrand and H.-J. Wunderlich, Test und Synthese schneller eingebetteter Systeme. Universität Stuttgart, 1998.
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