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165 Publications
2024 | Conference Paper | LibreCat-ID: 52744
Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations
H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, n.d., p. 6.
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H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, n.d., p. 6.
2024 | Conference Paper | LibreCat-ID: 52742
Vmin Testing under Variations: Defect vs. Fault Coverage
H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE, n.d., p. 6.
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H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE, n.d., p. 6.
2024 | Conference Paper | LibreCat-ID: 52743
Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle
S. Hellebrand, S. Sadeghi-Kohan, H.-J. Wunderlich, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.
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S. Hellebrand, S. Sadeghi-Kohan, H.-J. Wunderlich, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.
2024 | Conference Paper | LibreCat-ID: 52745
Robust Test of Small Delay Faults under PVT-Variations
H.-J. Wunderlich, H. Jafarzadeh, S. Hellebrand, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.
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H.-J. Wunderlich, H. Jafarzadeh, S. Hellebrand, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.
2024 | Misc | LibreCat-ID: 50284
Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression
A. Stiballe, J.D. Reimer, S. Sadeghi-Kohan, S. Hellebrand, Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024.
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A. Stiballe, J.D. Reimer, S. Sadeghi-Kohan, S. Hellebrand, Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024.
2023 | Misc | LibreCat-ID: 35204
On Cryptography Effects on Interconnect Reliability
A. Ghazal, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, On Cryptography Effects on Interconnect Reliability, 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, Erfurt, Germany, 2023.
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A. Ghazal, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, On Cryptography Effects on Interconnect Reliability, 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, Erfurt, Germany, 2023.
2023 | Dissertation | LibreCat-ID: 46482 | 
Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen
A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen, Universität Paderborn, Paderborn, 2023.
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A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen, Universität Paderborn, Paderborn, 2023.
2023 | Conference Paper | LibreCat-ID: 46739
Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023.
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S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023.
2023 | Conference Paper | LibreCat-ID: 46738
Optimizing the Streaming of Sensor Data with Approximate Communication
S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.
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S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.
2023 | Journal Article | LibreCat-ID: 46264
Workload-Aware Periodic Interconnect BIST
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &Test (2023) 1–1.
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S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &Test (2023) 1–1.
2023 | Conference Paper | LibreCat-ID: 45830
Robust Pattern Generation for Small Delay Faults under Process Variations
H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023.
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H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023.
2022 | Journal Article | LibreCat-ID: 29351
Stress-Aware Periodic Test of Interconnects
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).
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S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).
2022 | Misc | LibreCat-ID: 29890
EM-Aware Interconnect BIST
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online, 2022.
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S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online, 2022.
2020 | Conference Paper | LibreCat-ID: 19422
Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study
A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.
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A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.
2020 | Misc | LibreCat-ID: 15419
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
S. Sadeghi-Kohan, S. Hellebrand, Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects, 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, Ludwigsburg, 2020.
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S. Sadeghi-Kohan, S. Hellebrand, Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects, 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, Ludwigsburg, 2020.
2020 | Conference Paper | LibreCat-ID: 29200
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.
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S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.
2020 | Conference Paper | LibreCat-ID: 19421
Logic Fault Diagnosis of Hidden Delay Defects
S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020.
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S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020.
2019 | Misc | LibreCat-ID: 8112
A Hybrid Space Compactor for Varying X-Rates
M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), Prien am Chiemsee, 2019.
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M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), Prien am Chiemsee, 2019.
2019 | Journal Article | LibreCat-ID: 8667
Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test
A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28 (2019) 1–23.
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A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28 (2019) 1–23.
2019 | Journal Article | LibreCat-ID: 13048
Built-in Test for Hidden Delay Faults
M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968.
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M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968.
2019 | Conference Paper | LibreCat-ID: 12918
A Hybrid Space Compactor for Adaptive X-Handling
M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.
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M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.
2018 | Misc | LibreCat-ID: 4576
Stochastische Kompaktierung für den Hochgeschwindigkeitstest
A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest, 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), Freiburg, Germany, 2018.
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A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest, 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), Freiburg, Germany, 2018.
2018 | Journal Article | LibreCat-ID: 12974
Guest Editors' Introduction - Special Issue on Approximate Computing
S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich, IEEE Embedded Systems Letters 10 (2018) 1–1.
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S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich, IEEE Embedded Systems Letters 10 (2018) 1–1.
2018 | Journal Article | LibreCat-ID: 13057
Design For Small Delay Test - A Simulation Study
M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133.
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M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133.
2018 | Misc | LibreCat-ID: 13072
Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test, 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018.
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M. Kampmann, S. Hellebrand, Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test, 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018.
2018 | Conference Paper | LibreCat-ID: 29460
Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture
R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.
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R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.
2018 | Conference Paper | LibreCat-ID: 4575
Tuning Stochastic Space Compaction to Faster-than-at-Speed Test
A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest, Hungary, 2018.
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A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest, Hungary, 2018.
2018 | Conference Paper | LibreCat-ID: 10575
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention
C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in: 27th IEEE Asian Test Symposium (ATS’18), 2018.
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C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in: 27th IEEE Asian Test Symposium (ATS’18), 2018.
2018 | Conference Paper | LibreCat-ID: 29459
Near-Optimal Node Selection Procedure for Aging Monitor Placement
S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.
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S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.
2017 | Conference Paper | LibreCat-ID: 12973
Special Session on Early Life Failures
J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.
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J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.
2017 | Misc | LibreCat-ID: 13078
X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz
M. Kampmann, S. Hellebrand, X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz, 29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
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M. Kampmann, S. Hellebrand, X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz, 29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
2017 | Conference Paper | LibreCat-ID: 10576
Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, in: 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17), IEEE, 2017.
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M. Kampmann, S. Hellebrand, in: 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17), IEEE, 2017.
2017 | Journal Article | LibreCat-ID: 29462
Self-Adjusting Monitor for Measuring Aging Rate and Advancement
S. Sadeghi-Kohan, M. Kamal, Z. Navabi, IEEE Transactions on Emerging Topics in Computing 8 (2017) 627–641.
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S. Sadeghi-Kohan, M. Kamal, Z. Navabi, IEEE Transactions on Emerging Topics in Computing 8 (2017) 627–641.
2017 | Conference Paper | LibreCat-ID: 29463
Universal mitigation of NBTI-induced aging by design randomization
M. Jenihhin, A. Kamkin, Z. Navabi, S. Sadeghi-Kohan, in: 2016 IEEE East-West Design & Test Symposium (EWDTS), IEEE, 2017.
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M. Jenihhin, A. Kamkin, Z. Navabi, S. Sadeghi-Kohan, in: 2016 IEEE East-West Design & Test Symposium (EWDTS), IEEE, 2017.
2016 | Conference Paper | LibreCat-ID: 12975
X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, in: 25th IEEE Asian Test Symposium (ATS’16), IEEE, Hiroshima, Japan, 2016, pp. 1–6.
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M. Kampmann, S. Hellebrand, in: 25th IEEE Asian Test Symposium (ATS’16), IEEE, Hiroshima, Japan, 2016, pp. 1–6.
2015 | Conference Paper | LibreCat-ID: 12976
Optimized Selection of Frequencies for Faster-Than-at-Speed Test
M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, in: 24th IEEE Asian Test Symposium (ATS’15), IEEE, Mumbai, India, 2015, pp. 109–114.
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M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, in: 24th IEEE Asian Test Symposium (ATS’15), IEEE, Mumbai, India, 2015, pp. 109–114.
2015 | Journal Article | LibreCat-ID: 13056
A High Performance SEU Tolerant Latch
Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory and Applications (JETTA) 31 (2015) 349–359.
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Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory and Applications (JETTA) 31 (2015) 349–359.
2015 | Misc | LibreCat-ID: 13077
Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler
S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H.-J. Wunderlich, Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler, 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
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S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H.-J. Wunderlich, Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler, 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
2015 | Conference Paper | LibreCat-ID: 29465
Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation
S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, Z. Navabi, in: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.
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S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, Z. Navabi, in: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.
2015 | Conference Paper | LibreCat-ID: 29466
Online self adjusting progressive age monitoring of timing variations
S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, Z. Navabi, in: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.
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S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, Z. Navabi, in: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.
2014 | Conference Paper | LibreCat-ID: 12977
FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects
S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’14), IEEE, Seattle, Washington, USA, 2014.
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S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’14), IEEE, Seattle, Washington, USA, 2014.
2014 | Journal Article | LibreCat-ID: 13054
SAT-Based ATPG beyond Stuck-at Fault Testing
S. Hellebrand, H.-J. Wunderlich, DeGruyter Journal on Information Technology (It) 56 (2014) 165–172.
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S. Hellebrand, H.-J. Wunderlich, DeGruyter Journal on Information Technology (It) 56 (2014) 165–172.
2014 | Journal Article | LibreCat-ID: 13055
Adaptive Bayesian Diagnosis of Intermittent Faults
L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 30 (2014) 527–540.
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L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 30 (2014) 527–540.
2014 | Journal Article | LibreCat-ID: 46266
A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs
B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers (2014) 1–1.
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B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers (2014) 1–1.
2014 | Conference Paper | LibreCat-ID: 46268
An off-line MDSI interconnect BIST incorporated in BS 1149.1
M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, Z. Navabi, in: 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014.
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M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, Z. Navabi, in: 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014.
2014 | Conference Paper | LibreCat-ID: 46267
Improving polynomial datapath debugging with HEDs
S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, Z. Navabi, in: 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014.
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S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, Z. Navabi, in: 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014.
2013 | Conference Paper | LibreCat-ID: 12979
Analyzing and Quantifying Fault Tolerance Properties
S. Hellebrand, in: 14th IEEE Latin American Test Workshop - (LATW’13), IEEE, Cordoba, Argentina, 2013.
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S. Hellebrand, in: 14th IEEE Latin American Test Workshop - (LATW’13), IEEE, Cordoba, Argentina, 2013.
2013 | Misc | LibreCat-ID: 13075
Adaptive Test and Diagnosis of Intermittent Faults
A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, Adaptive Test and Diagnosis of Intermittent Faults, 14th Latin American Test Workshop, Cordoba, Argentina, 2013.
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A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, Adaptive Test and Diagnosis of Intermittent Faults, 14th Latin American Test Workshop, Cordoba, Argentina, 2013.
2013 | Conference Paper | LibreCat-ID: 46271
BS 1149.1 extensions for an online interconnect fault detection and recovery
S. Sadeghi-Kohan, M. Namaki-Shoushtari, F. Javaheri, Z. Navabi, in: 2012 IEEE International Test Conference, IEEE, 2013.
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S. Sadeghi-Kohan, M. Namaki-Shoushtari, F. Javaheri, Z. Navabi, in: 2012 IEEE International Test Conference, IEEE, 2013.
2013 | Conference Paper | LibreCat-ID: 46270
A new structure for interconnect offline testing
S. Sadeghi-Kohan, S. Keshavarz, F. Zokaee, F. Farahmandi, Z. Navabi, in: East-West Design & Test Symposium (EWDTS 2013), IEEE, 2013.
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S. Sadeghi-Kohan, S. Keshavarz, F. Zokaee, F. Farahmandi, Z. Navabi, in: East-West Design & Test Symposium (EWDTS 2013), IEEE, 2013.
2012 | Conference Paper | LibreCat-ID: 12980
Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test
A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, H.-J. Wunderlich, in: 13th IEEE Latin American Test Workshop (LATW’12), IEEE, Quito, Ecuador, 2012, pp. 1–4.
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A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, H.-J. Wunderlich, in: 13th IEEE Latin American Test Workshop (LATW’12), IEEE, Quito, Ecuador, 2012, pp. 1–4.
2012 | Conference Paper | LibreCat-ID: 12981
Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test
A. Cook, S. Hellebrand, H.-J. Wunderlich, in: 17th IEEE European Test Symposium (ETS’12), IEEE, Annecy, France, 2012, pp. 1–6.
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A. Cook, S. Hellebrand, H.-J. Wunderlich, in: 17th IEEE European Test Symposium (ETS’12), IEEE, Annecy, France, 2012, pp. 1–6.
2012 | Misc | LibreCat-ID: 13074
Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern
A. Cook, S. Hellebrand, H.-J. Wunderlich, Eingebaute Selbstdiagnose Mit Zufälligen Und Deterministischen Mustern, 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany, 2012.
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A. Cook, S. Hellebrand, H.-J. Wunderlich, Eingebaute Selbstdiagnose Mit Zufälligen Und Deterministischen Mustern, 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany, 2012.
2011 | Conference Paper | LibreCat-ID: 12982
Diagnostic Test of Robust Circuits
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 20th IEEE Asian Test Symposium (ATS’11), IEEE, New Delhi, India, 2011, pp. 285–290.
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A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 20th IEEE Asian Test Symposium (ATS’11), IEEE, New Delhi, India, 2011, pp. 285–290.
2011 | Conference Paper | LibreCat-ID: 12984
Towards Variation-Aware Test Methods
I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, P. Maxwell, in: 16th IEEE European Test Symposium Trondheim (ETS’11), IEEE, Trondheim, Norway, 2011.
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I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, P. Maxwell, in: 16th IEEE European Test Symposium Trondheim (ETS’11), IEEE, Trondheim, Norway, 2011.
2011 | Conference Paper | LibreCat-ID: 13053
Robuster Selbsttest mit Diagnose
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf,” Hamburg, Germany, 2011, pp. 48–53.
LibreCat
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf,” Hamburg, Germany, 2011, pp. 48–53.
2011 | Journal Article | LibreCat-ID: 13052
Variation-Aware Fault Modeling
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer 54 (2011) 1813–1826.
LibreCat
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer 54 (2011) 1813–1826.
2011 | Conference Paper | LibreCat-ID: 46272
Virtual tester development using HDL/PLI
A. Kamran, N. Nemati, S. Sadeghi-Kohan, Z. Navabi, in: 2010 East-West Design & Test Symposium (EWDTS), IEEE, 2011.
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A. Kamran, N. Nemati, S. Sadeghi-Kohan, Z. Navabi, in: 2010 East-West Design & Test Symposium (EWDTS), IEEE, 2011.
2010 | Misc | LibreCat-ID: 10670
Testdatenkompression mit Hilfe der Netzwerkinfrastruktur
V. Fröse, R. Ibers, S. Hellebrand, Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur, 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
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V. Fröse, R. Ibers, S. Hellebrand, Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur, 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
2010 | Conference Paper | LibreCat-ID: 12987
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), IEEE, Chicago, IL, USA, 2010.
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B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), IEEE, Chicago, IL, USA, 2010.
2010 | Conference Paper | LibreCat-ID: 13051
Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz
M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 81–88.
LibreCat
M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 81–88.
2010 | Misc | LibreCat-ID: 13073
Nano-Electronic Systems
S. Hellebrand, Nano-Electronic Systems, Editorial, it 4/2010, pp. 179-180, 2010.
LibreCat
S. Hellebrand, Nano-Electronic Systems, Editorial, it 4/2010, pp. 179-180, 2010.
2010 | Conference Paper | LibreCat-ID: 12983
Variation-Aware Fault Modeling
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 19th IEEE Asian Test Symposium (ATS’10), IEEE, Shanghai, China, 2010, pp. 87–93.
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| DOI
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 19th IEEE Asian Test Symposium (ATS’10), IEEE, Shanghai, China, 2010, pp. 87–93.
2010 | Conference Paper | LibreCat-ID: 12985
Efficient Test Response Compaction for Robust BIST Using Parity Sequences
T. Indlekofer, M. Schnittger, S. Hellebrand, in: 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, Amsterdam, The Netherlands, 2010, pp. 480–485.
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T. Indlekofer, M. Schnittger, S. Hellebrand, in: 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, Amsterdam, The Netherlands, 2010, pp. 480–485.
2010 | Conference Paper | LibreCat-ID: 12986
The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems
M. Hunger, S. Hellebrand, in: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, Kyoto, Japan, 2010, pp. 101–108.
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M. Hunger, S. Hellebrand, in: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, Kyoto, Japan, 2010, pp. 101–108.
2010 | Conference Paper | LibreCat-ID: 12988
Reusing NoC-Infrastructure for Test Data Compression
V. Froese, R. Ibers, S. Hellebrand, in: 28th IEEE VLSI Test Symposium (VTS’10), IEEE, Santa Cruz, CA, USA, 2010, pp. 227–231.
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V. Froese, R. Ibers, S. Hellebrand, in: 28th IEEE VLSI Test Symposium (VTS’10), IEEE, Santa Cruz, CA, USA, 2010, pp. 227–231.
2010 | Conference Paper | LibreCat-ID: 13049
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), Chicago, IL, USA, 2010.
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B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), Chicago, IL, USA, 2010.
2010 | Conference Paper | LibreCat-ID: 13050
Robuster Selbsttest mit extremer Kompaktierung
T. Indlekofer, M. Schnittger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 17–24.
LibreCat
T. Indlekofer, M. Schnittger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 17–24.
2009 | Conference Paper | LibreCat-ID: 12991
ATPG-Based Grading of Strong Fault-Secureness
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, Sesimbra-Lisbon, Portugal, 2009.
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M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, Sesimbra-Lisbon, Portugal, 2009.
2009 | Conference Paper | LibreCat-ID: 12990
Are Robust Circuits Really Robust?
S. Hellebrand, M. Hunger, in: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, Chicago, IL, USA, 2009, p. 77.
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S. Hellebrand, M. Hunger, in: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, Chicago, IL, USA, 2009, p. 77.
2009 | Conference Paper | LibreCat-ID: 13030
Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Stuttgart, Germany, 2009.
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M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Stuttgart, Germany, 2009.
2008 | Misc | LibreCat-ID: 13033
Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit
T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, C. G. Zoellin, Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008.
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T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, C. G. Zoellin, Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008.
2008 | Misc | LibreCat-ID: 13035
Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen
U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008.
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U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008.
2008 | Conference Paper | LibreCat-ID: 12992
A Modular Memory BIST for Optimized Memory Repair
P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, Rhodos, Greece, 2008.
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P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, Rhodos, Greece, 2008.
2008 | Conference Paper | LibreCat-ID: 12994
Signature Rollback - A Technique for Testing Robust Circuits
U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, in: 26th IEEE VLSI Test Symposium (VTS’08), IEEE, San Diego, CA, USA, 2008, pp. 125–130.
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U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, in: 26th IEEE VLSI Test Symposium (VTS’08), IEEE, San Diego, CA, USA, 2008, pp. 125–130.
2008 | Conference Paper | LibreCat-ID: 12993
Verification and Analysis of Self-Checking Properties through ATPG
M. Hunger, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, Rhodos, Greece, 2008.
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M. Hunger, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, Rhodos, Greece, 2008.
2008 | Conference Paper | LibreCat-ID: 13031
Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG
M. Hunger, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.
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M. Hunger, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.
2008 | Conference Paper | LibreCat-ID: 13032
Modularer Selbsttest und optimierte Reparaturanalyse
P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.
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P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.
2007 | Misc | LibreCat-ID: 13038
Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing
S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing, 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk), 2007.
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S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing, 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk), 2007.
2007 | Misc | LibreCat-ID: 13039
An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips, DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.
LibreCat
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips, DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.
2007 | Misc | LibreCat-ID: 13042
An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
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P. Oehler, S. Hellebrand, H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
2007 | Misc | LibreCat-ID: 13043
Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden
S. Hellebrand, Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden, ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
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S. Hellebrand, Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden, ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
2007 | Conference Paper | LibreCat-ID: 12995
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), IEEE, Rome, Italy, 2007, pp. 50–58.
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S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), IEEE, Rome, Italy, 2007, pp. 50–58.
2007 | Conference Paper | LibreCat-ID: 12996
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, Krakow, Poland, 2007, pp. 185–190.
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P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, Krakow, Poland, 2007, pp. 185–190.
2007 | Conference Paper | LibreCat-ID: 12997
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 12th IEEE European Test Symposium (ETS’07), IEEE, Freiburg, Germany, 2007, pp. 91–96.
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P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 12th IEEE European Test Symposium (ETS’07), IEEE, Freiburg, Germany, 2007, pp. 91–96.
2007 | Conference Paper | LibreCat-ID: 13037
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper), Bled, Slovenia, 2007.
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S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper), Bled, Slovenia, 2007.
2007 | Journal Article | LibreCat-ID: 13036
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, Informacije MIDEM, Ljubljana (Invited Paper) 37 (2007) 212–219.
LibreCat
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, Informacije MIDEM, Ljubljana (Invited Paper) 37 (2007) 212–219.
2007 | Journal Article | LibreCat-ID: 13044
An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip
M. Ali, S. Hessler, M. Welzl, S. Hellebrand, International Journal on High Performance Systems Architecture 1 (2007) 113–123.
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M. Ali, S. Hessler, M. Welzl, S. Hellebrand, International Journal on High Performance Systems Architecture 1 (2007) 113–123.
2007 | Conference Paper | LibreCat-ID: 13040
A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, in: 4th International Conference on Information Technology: New Generations (ITNG’07), Las Vegas, Nevada, USA, 2007, pp. 1027–1032.
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M. Ali, M. Welzl, S. Hessler, S. Hellebrand, in: 4th International Conference on Information Technology: New Generations (ITNG’07), Las Vegas, Nevada, USA, 2007, pp. 1027–1032.
2007 | Conference Paper | LibreCat-ID: 13041
Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, in: 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Munich, Germany, 2007.
LibreCat
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, in: 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Munich, Germany, 2007.
2006 | Journal Article | LibreCat-ID: 13045
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, It - Information Technology 48 (2006) 305–311.
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B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, It - Information Technology 48 (2006) 305–311.
2005 | Misc | LibreCat-ID: 13046
A Low Power Design for Embedded DRAMs with Online Consistency Checking
P. Oehler, S. Hellebrand, A Low Power Design for Embedded DRAMs with Online Consistency Checking, Kleinheubachertagung 2005, Miltenberg, Germany, 2005.
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P. Oehler, S. Hellebrand, A Low Power Design for Embedded DRAMs with Online Consistency Checking, Kleinheubachertagung 2005, Miltenberg, Germany, 2005.
2005 | Misc | LibreCat-ID: 13101
Dynamic Routing: A Prerequisite for Reliable NoCs
M. Ali, M. Welzl, S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
LibreCat
M. Ali, M. Welzl, S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
2005 | Misc | LibreCat-ID: 13102
Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study
P. Oehler, S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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P. Oehler, S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
2005 | Conference Paper | LibreCat-ID: 12999
Considerations for Fault-Tolerant Networks on Chips
M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: IEEE International Conference on Microelectronics (ICM’05), IEEE, Islamabad, Pakistan, 2005.
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M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: IEEE International Conference on Microelectronics (ICM’05), IEEE, Islamabad, Pakistan, 2005.
2005 | Conference Paper | LibreCat-ID: 13000
Low Power Embedded DRAMs with High Quality Error Correcting Capabilities
P. Oehler, S. Hellebrand, in: 10th IEEE European Test Symposium (ETS’05), IEEE, Tallinn, Estonia, 2005, pp. 148–153.
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P. Oehler, S. Hellebrand, in: 10th IEEE European Test Symposium (ETS’05), IEEE, Tallinn, Estonia, 2005, pp. 148–153.
2005 | Conference Paper | LibreCat-ID: 12998
A Dynamic Routing Mechanism for Network on Chip
M. Ali, M. Welzl, S. Hellebrand, in: 23rd IEEE NORCHIP Conference, IEEE, Oulu, Finland, 2005, pp. 70–73.
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M. Ali, M. Welzl, S. Hellebrand, in: 23rd IEEE NORCHIP Conference, IEEE, Oulu, Finland, 2005, pp. 70–73.
2004 | Conference Paper | LibreCat-ID: 13071
Sensor Networks with More Features Using Less Hardware
M. Liu Jing, S. Ruehrup, C. Schindelhauer, K. Volbert, M. Dierkes, A. Bellgardt, R. Ibers, U. Hilleringmann, in: {GOR/NGB Conference Tilburg 2004}, Tilburg, Netherlands, 2004.
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M. Liu Jing, S. Ruehrup, C. Schindelhauer, K. Volbert, M. Dierkes, A. Bellgardt, R. Ibers, U. Hilleringmann, in: {GOR/NGB Conference Tilburg 2004}, Tilburg, Netherlands, 2004.
2004 | Misc | LibreCat-ID: 13099
Im Westen viel Neues - Informatik an der Universität Innsbruck
R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, O. Scherzer, Im Westen Viel Neues - Informatik an Der Universität Innsbruck, OCG Journal, pp. 28-29, 2004.
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R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, O. Scherzer, Im Westen Viel Neues - Informatik an Der Universität Innsbruck, OCG Journal, pp. 28-29, 2004.
2004 | Misc | LibreCat-ID: 13100
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
S. Hellebrand, A. Wuertenberger, C. S. Tautermann, Data Compression for Multiple Scan Chains Using Dictionaries with Corrections, 9th IEEE European Test Symposium, Ajaccio, Corsica, France, 2004.
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S. Hellebrand, A. Wuertenberger, C. S. Tautermann, Data Compression for Multiple Scan Chains Using Dictionaries with Corrections, 9th IEEE European Test Symposium, Ajaccio, Corsica, France, 2004.