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165 Publications
1998 | Misc | LibreCat-ID: 13091
N. Yarmolik, V., Hellebrand, S., & Wunderlich, H.-J. (1998). Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
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1998 | Misc | LibreCat-ID: 13092
N. Yarmolik, V., Hellebrand, S., & Wunderlich, H.-J. (1998). Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop.
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1998 | Book Chapter | LibreCat-ID: 13060
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1998). Mixed-Mode BIST Using Embedded Processors. In Mixed-Mode BIST Using Embedded Processors. Kluwer Academic Publishers.
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1998 | Journal Article | LibreCat-ID: 13061
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1998). Mixed-Mode BIST Using Embedded Processors. Journal of Electronic Testing Theory and Applications - JETTA, 12(1/2), 127–138.
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1998 | Journal Article | LibreCat-ID: 13064
Hellebrand, S., Hertwig, A., & Wunderlich, H.-J. (1998). Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. IEEE Design and Test, 15(4), 36–41.
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1998 | Conference Paper | LibreCat-ID: 13007
Hertwig, A., Hellebrand, S., & Wunderlich, H.-J. (1998). Fast Self-Recovering Controllers. 16th IEEE VLSI Test Symposium (VTS’98), 296–302. https://doi.org/10.1109/vtest.1998.670883
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1998 | Conference Paper | LibreCat-ID: 13008
Hellebrand, S., Wunderlich, H.-J., & N. Yarmolik, V. (1998). Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. Design Automation and Test in Europe (DATE’98), 173–179. https://doi.org/10.1109/date.1998.655853
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1998 | Conference Paper | LibreCat-ID: 13063
N. Yarmolik, V., V. Klimets, Y., Hellebrand, S., & Wunderlich, H.-J. (1998). New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. Design & Diagnostics of Electronic Circuits & Systems (DDECS’98), 27–33.
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1997 | Misc | LibreCat-ID: 13089
Tsai, K.-H., Hellebrand, S., Rajski, J., & Marek-Sadowska, M. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
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1997 | Misc | LibreCat-ID: 13090
Hertwig, A., Hellebrand, S., & Wunderlich, H.-J. (1997). Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece.
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1997 | Conference Paper | LibreCat-ID: 13009
Tsai, K.-H., Hellebrand, S., Marek-Sadowska, M., & Rajski, J. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. 34th ACM/IEEE Design Automation Conference (DAC’97). https://doi.org/10.1109/dac.1997.597194
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1996 | Misc | LibreCat-ID: 13087
Hellebrand, S., & Wunderlich, H.-J. (1996). Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA.
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1996 | Misc | LibreCat-ID: 13088
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France.
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1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. IEEE International Test Conference (ITC’96), 195–204. https://doi.org/10.1109/test.1996.556962
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1995 | Report | LibreCat-ID: 13026
Hellebrand, S., & Wunderlich, H.-J. (1995). Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany.
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1995 | Report | LibreCat-ID: 13027
Hellebrand, S., Wunderlich, H.-J., Goncalves, F., & Paulo Teixeira, J. (1995). Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany.
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1995 | Report | LibreCat-ID: 13028
Hellebrand, S., Herzog, M., & Wunderlich, H.-J. (1995). Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany.
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1995 | Misc | LibreCat-ID: 13086
Hellebrand, S., Reeb, B., Tarnick, S., & Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA.
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1995 | Journal Article | LibreCat-ID: 13011
Hellebrand, S., Rajski, J., Tarnick, S., Venkataraman, S., & Courtois, B. (1995). Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers, 44(2), 223–233. https://doi.org/10.1109/12.364534
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1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand, S., Reeb, B., Tarnick, S., & Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 88–94. https://doi.org/10.1109/iccad.1995.479997
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1994 | Report | LibreCat-ID: 13024
Hellebrand, S., Juergensen, A., & Wunderlich, H.-J. (1994). Synthesis for Off-line Testability. University of Siegen, Germany.
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1994 | Report | LibreCat-ID: 13025
Hellebrand, S., Juergensen, A., Stroele, A., & Wunderlich, H.-J. (1994). Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany.
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1994 | Misc | LibreCat-ID: 13083
Venkataraman, S., Rajski, J., Hellebrand, S., & Tarnick, S. (1994). Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.
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1994 | Misc | LibreCat-ID: 13084
Hellebrand, S., & Wunderlich, H.-J. (1994). Ein Verfahren zur testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.
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1994 | Misc | LibreCat-ID: 13085
Hellebrand, S., Paulo Teixeira, J., & Wunderlich, H.-J. (1994). Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
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1994 | Conference Paper | LibreCat-ID: 13014
Hellebrand, S., & Wunderlich, H.-J. (1994). An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 110–116. https://doi.org/10.1109/iccad.1994.629752
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1994 | Conference Paper | LibreCat-ID: 13059
Hellebrand, S., & Wunderlich, H.-J. (1994). Synthese schneller selbsttestbarer Steuerwerke. Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 3–11.
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1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand, S., & Wunderlich, H.-J. (1994). Synthesis of Self-Testable Controllers. European Design and Test Conference (EDAC/ETC/EUROASIC), 580–585. https://doi.org/10.1109/edtc.1994.326815
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1993 | Misc | LibreCat-ID: 13081
Hellebrand, S., Tarnick, S., Rajski, J., & Courtois, B. (1993). Effiziente Erzeugung deterministischer Muster im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany.
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1993 | Misc | LibreCat-ID: 13082
Hellebrand, S., & Wunderlich, H.-J. (1993). Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France.
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1993 | Conference Paper | LibreCat-ID: 13015
Venkataraman, S., Rajski, J., Hellebrand, S., & Tarnick, S. (1993). An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers. ACM/IEEE International Conference on Computer Aided Design (ICCAD’93). https://doi.org/10.1109/iccad.1993.580117
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1992 | Report | LibreCat-ID: 13023
Hellebrand, S., Tarnick, S., Rajski, J., & Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Institut National Polytechnique de Grenoble, Grenoble, France.
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1992 | Misc | LibreCat-ID: 13076
Hellebrand, S., Tarnick, S., Rajski, J., & Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. IEEE Design for Testability Workshop, Vail, CO, USA.
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1992 | Misc | LibreCat-ID: 13080
Hellebrand, S., Tarnick, S., Rajski, J., & Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Workshop on New Directions for Testing, Montreal, Canada.
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1992 | Journal Article | LibreCat-ID: 13017
Wunderlich, H.-J., & Hellebrand, S. (1992). The Pseudoexhaustive Test of Sequential Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 11(1), 26–33. https://doi.org/10.1109/43.108616
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1992 | Conference Paper | LibreCat-ID: 13016
Hellebrand, S., Tarnick, S., Rajski, J., & Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE International Test Conference (ITC’92), 120–129. https://doi.org/10.1109/test.1992.527812
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1991 | Book | LibreCat-ID: 13034
Hellebrand, S. (1991). Synthese vollständig testbarer Schaltungen. Verlag Düsseldorf: VDI Verlag: Verlag Düsseldorf: VDI Verlag.
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1990 | Misc | LibreCat-ID: 13103
Hellebrand, S., Wunderlich, H.-J., & F. Haberl, O. (1990). Generating Pseudo-Exhaustive Vectors for External Testing. IEEE Design for Testability Workshop, Vail, CO, USA.
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1990 | Conference Paper | LibreCat-ID: 13018
Hellebrand, S., & Wunderlich, H.-J. (1990). Tools and Devices Supporting the Pseudo-Exhaustive Test. European Design Automation Conference (EDAC’90), 13–17. https://doi.org/10.1109/edac.1990.136612
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1990 | Conference Paper | LibreCat-ID: 13019
Hellebrand, S., Wunderlich, H.-J., & F. Haberl, O. (1990). Generating Pseudo-Exhaustive Vectors for External Testing. IEEE International Test Conference (ITC’90), 670–679. https://doi.org/10.1109/test.1990.114082
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1989 | Conference Paper | LibreCat-ID: 13020
Wunderlich, H.-J., & Hellebrand, S. (1989). The Pseudo-Exhaustive Test of Sequential Circuits. IEEE International Test Conference (ITC’89), 19–27. https://doi.org/10.1109/test.1989.82273
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1988 | Conference Paper | LibreCat-ID: 13021
Wunderlich, H.-J., & Hellebrand, S. (1988). Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits. 18th International Symposium on Fault-Tolerant Computing, FTCS-18, 36–45. https://doi.org/10.1109/ftcs.1988.5294
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1988 | Conference Paper | LibreCat-ID: 13058
Schmid, D., Wunderlich, H.-J., Feldbusch, F., Hellebrand, S., Holzinger, J., & Kunzmann, A. (1988). Integrated Tools for Automatic Design for Testability. Tool Integration and Design Environments, F.J. Rammig (Editor), 233–258.
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1988 | Conference Paper | LibreCat-ID: 13062
Hellebrand, S., & Wunderlich, H.-J. (1988). Automatisierung des Entwurfs vollständig testbarer Schaltungen. GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, 145–159.
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1986 | Report | LibreCat-ID: 13022
Hellebrand, S. (1986). Deformation dicker Punkte und Netze von Quadriken. Universität Regensburg, Fakultät für Mathematik, Regensburg, Germany.
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