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136 Publications


2013 | Misc | LibreCat-ID: 13075
Adaptive Test and Diagnosis of Intermittent Faults
A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, Adaptive Test and Diagnosis of Intermittent Faults, 14th Latin American Test Workshop, Cordoba, Argentina, 2013.
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2013 | Conference Paper | LibreCat-ID: 12979
Analyzing and Quantifying Fault Tolerance Properties
S. Hellebrand, in: {14th IEEE Latin American Test Workshop - (LATW’13)}, {IEEE}, Cordoba, Argentina, 2013.
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2012 | Conference Paper | LibreCat-ID: 12980
Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test
A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, H.-J. Wunderlich, in: {13th IEEE Latin American Test Workshop (LATW’12)}, {IEEE}, Quito, Ecuador, 2012, pp. 1–4.
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2012 | Conference Paper | LibreCat-ID: 12981
Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test
A. Cook, S. Hellebrand, H.-J. Wunderlich, in: {17th IEEE European Test Symposium (ETS’12)}, {IEEE}, Annecy, France, 2012, pp. 1–6.
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2012 | Misc | LibreCat-ID: 13074
Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern
A. Cook, S. Hellebrand, H.-J. Wunderlich, Eingebaute Selbstdiagnose Mit Zufälligen Und Deterministischen Mustern, 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany, 2012.
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2011 | Conference Paper | LibreCat-ID: 12984
Towards Variation-Aware Test Methods
I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, P. Maxwell, in: {16th IEEE European Test Symposium Trondheim (ETS’11),(Embedded Tutorial)}, {IEEE}, Trondheim, Norway, 2011.
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2011 | Journal Article | LibreCat-ID: 13052
Variation-Aware Fault Modeling
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, {SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer} 54 (2011) 1813–1826.
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2011 | Conference Paper | LibreCat-ID: 13053
Robuster Selbsttest mit Diagnose
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: {5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf”}, Hamburg, Germany, 2011, pp. 48–53.
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2011 | Conference Paper | LibreCat-ID: 12982
Diagnostic Test of Robust Circuits
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: {20th IEEE Asian Test Symposium (ATS’11)}, {IEEE}, New Delhi, India, 2011, pp. 285–290.
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2010 | Conference Paper | LibreCat-ID: 12983
Variation-Aware Fault Modeling
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: {19th IEEE Asian Test Symposium (ATS’10)}, {IEEE}, Shanghai, China, 2010, pp. 87–93.
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2010 | Conference Paper | LibreCat-ID: 12988
Reusing NoC-Infrastructure for Test Data Compression
V. Froese, R. Ibers, S. Hellebrand, in: {28th IEEE VLSI Test Symposium (VTS’10)}, {IEEE}, Santa Cruz, CA, USA, 2010, pp. 227–231.
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2010 | Conference Paper | LibreCat-ID: 13049
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: {4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}, Chicago, IL, USA, 2010.
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2010 | Conference Paper | LibreCat-ID: 13051
Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz
M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 81–88.
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2010 | Conference Paper | LibreCat-ID: 12985
Efficient Test Response Compaction for Robust BIST Using Parity Sequences
T. Indlekofer, M. Schnittger, S. Hellebrand, in: {28th IEEE International Conference on Computer Design (ICCD’10)}, {IEEE}, Amsterdam, The Netherlands, 2010, pp. 480–485.
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2010 | Conference Paper | LibreCat-ID: 12986
The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems
M. Hunger, S. Hellebrand, in: {25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)}, {IEEE}, Kyoto, Japan, 2010, pp. 101–108.
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2010 | Misc | LibreCat-ID: 10670
Testdatenkompression mit Hilfe der Netzwerkinfrastruktur
V. Fröse, R. Ibers, S. Hellebrand, Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur, 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
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2010 | Misc | LibreCat-ID: 13073
Nano-Electronic Systems
S. Hellebrand, Nano-Electronic Systems, Editorial, it 4/2010, pp. 179-180, 2010.
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2010 | Conference Paper | LibreCat-ID: 12987
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: {40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10)}, {IEEE}, Chicago, IL, USA, 2010.
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2010 | Conference Paper | LibreCat-ID: 13050
Robuster Selbsttest mit extremer Kompaktierung
T. Indlekofer, M. Schnittger, S. Hellebrand, in: {4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Wildbad Kreuth, Germany, 2010, pp. 17–24.
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2009 | Conference Paper | LibreCat-ID: 12990
Are Robust Circuits Really Robust?
S. Hellebrand, M. Hunger, in: {24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)}, {IEEE}, Chicago, IL, USA, 2009, p. 77.
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2009 | Conference Paper | LibreCat-ID: 12991
ATPG-Based Grading of Strong Fault-Secureness
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: {15th IEEE International On-Line Testing Symposium (IOLTS’09)}, {IEEE}, Sesimbra-Lisbon, Portugal, 2009.
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2009 | Conference Paper | LibreCat-ID: 13030
Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: {3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Stuttgart, Germany, 2009.
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2008 | Conference Paper | LibreCat-ID: 13032
Modularer Selbsttest und optimierte Reparaturanalyse
P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: {2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Ingolstadt, Germany, 2008.
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2008 | Misc | LibreCat-ID: 13033
Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit
T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, C. G. Zoellin, Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008.
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2008 | Conference Paper | LibreCat-ID: 12992
A Modular Memory BIST for Optimized Memory Repair
P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: {14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)}, {IEEE}, Rhodos, Greece, 2008.
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2008 | Conference Paper | LibreCat-ID: 12993
Verification and Analysis of Self-Checking Properties through ATPG
M. Hunger, S. Hellebrand, in: {14th IEEE International On-Line Testing Symposium (IOLTS’08)}, {IEEE}, Rhodos, Greece, 2008.
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2008 | Misc | LibreCat-ID: 13035
Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen
U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008.
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2008 | Conference Paper | LibreCat-ID: 12994
Signature Rollback - A Technique for Testing Robust Circuits
U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, in: {26th IEEE VLSI Test Symposium (VTS’08)}, {IEEE}, San Diego, CA, USA, 2008, pp. 125–130.
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2008 | Conference Paper | LibreCat-ID: 13031
Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG
M. Hunger, S. Hellebrand, in: {2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Ingolstadt, Germany, 2008.
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2007 | Conference Paper | LibreCat-ID: 12995
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: {22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07)}, {IEEE}, Rome, Italy, 2007, pp. 50–58.
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2007 | Conference Paper | LibreCat-ID: 13037
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: {43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper)}, Bled, Slovenia, 2007.
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2007 | Journal Article | LibreCat-ID: 13044
An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip
M. Ali, S. Hessler, M. Welzl, S. Hellebrand, {International Journal on High Performance Systems Architecture} 1 (2007) 113–123.
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2007 | Conference Paper | LibreCat-ID: 12996
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: {10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)}, {IEEE}, Krakow, Poland, 2007, pp. 185–190.
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2007 | Conference Paper | LibreCat-ID: 13040
A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, in: {4th International Conference on Information Technology: New Generations (ITNG’07)}, Las Vegas, Nevada, USA, 2007, pp. 1027–1032.
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2007 | Misc | LibreCat-ID: 13038
Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing
S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing, 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk), 2007.
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2007 | Conference Paper | LibreCat-ID: 12997
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: {12th IEEE European Test Symposium (ETS’07)}, {IEEE}, Freiburg, Germany, 2007, pp. 91–96.
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2007 | Conference Paper | LibreCat-ID: 13041
Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, in: {1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Munich, Germany, 2007.
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2007 | Misc | LibreCat-ID: 13039
An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips, DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.
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2007 | Misc | LibreCat-ID: 13042
An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
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2007 | Journal Article | LibreCat-ID: 13036
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, {Informacije MIDEM, Ljubljana (Invited Paper)} 37 (2007) 212–219.
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2007 | Misc | LibreCat-ID: 13043
Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden
S. Hellebrand, Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden, ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
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2006 | Journal Article | LibreCat-ID: 13045
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, {it -Information Technology} 48 (2006) 305–311.
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2005 | Misc | LibreCat-ID: 13102
Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study
P. Oehler, S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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2005 | Misc | LibreCat-ID: 13046
A Low Power Design for Embedded DRAMs with Online Consistency Checking
P. Oehler, S. Hellebrand, A Low Power Design for Embedded DRAMs with Online Consistency Checking, Kleinheubachertagung 2005, Miltenberg, Germany, 2005.
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2005 | Conference Paper | LibreCat-ID: 12998
A Dynamic Routing Mechanism for Network on Chip
M. Ali, M. Welzl, S. Hellebrand, in: {23rd IEEE NORCHIP Conference}, {IEEE}, Oulu, Finland, 2005, pp. 70–73.
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2005 | Conference Paper | LibreCat-ID: 13000
Low Power Embedded DRAMs with High Quality Error Correcting Capabilities
P. Oehler, S. Hellebrand, in: {10th IEEE European Test Symposium (ETS’05)}, {IEEE}, Tallinn, Estonia, 2005, pp. 148–153.
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2005 | Conference Paper | LibreCat-ID: 12999
Considerations for Fault-Tolerant Networks on Chips
M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: {IEEE International Conference on Microelectronics (ICM’05)}, {IEEE}, Islamabad, Pakistan, 2005.
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2005 | Misc | LibreCat-ID: 13101
Dynamic Routing: A Prerequisite for Reliable NoCs
M. Ali, M. Welzl, S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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2004 | Conference Paper | LibreCat-ID: 13001
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: {IEEE International Test Conference (ITC’04)}, {IEEE}, Charlotte, NC, USA, 2004, pp. 926–935.
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2004 | Misc | LibreCat-ID: 13099
Im Westen viel Neues - Informatik an der Universität Innsbruck
R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, O. Scherzer, Im Westen Viel Neues - Informatik an Der Universität Innsbruck, OCG Journal, pp. 28-29, 2004.
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