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165 Publications
2019 | Conference Paper | LibreCat-ID: 12918
Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. 50th IEEE International Test Conference (ITC), 1–8.
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2018 | Misc | LibreCat-ID: 4576
Sprenger, A., & Hellebrand, S. (2018). Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).
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2018 | Journal Article | LibreCat-ID: 12974
Hellebrand, S., Henkel, J., Raghunathan, A., & Wunderlich, H.-J. (2018). Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters, 10(1), 1–1. https://doi.org/10.1109/les.2018.2789942
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2018 | Journal Article | LibreCat-ID: 13057
Kampmann, M., & Hellebrand, S. (2018). Design For Small Delay Test - A Simulation Study. Microelectronics Reliability, 80, 124–133.
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2018 | Misc | LibreCat-ID: 13072
Kampmann, M., & Hellebrand, S. (2018). Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China.
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2018 | Conference Paper | LibreCat-ID: 29460
Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., & Navabi, Z. (2018). Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. Proceedings of the 2018 on Great Lakes Symposium on VLSI. https://doi.org/10.1145/3194554.3194599
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2018 | Conference Paper | LibreCat-ID: 4575
Sprenger, A., & Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). https://doi.org/10.1109/ddecs.2018.00020
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2018 | Conference Paper | LibreCat-ID: 10575
Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., & Wunderlich, H.-J. (2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. 27th IEEE Asian Test Symposium (ATS’18). https://doi.org/10.1109/ats.2018.00028
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2018 | Conference Paper | LibreCat-ID: 29459
Sadeghi-Kohan, S., Vafaei, A., & Navabi, Z. (2018). Near-Optimal Node Selection Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). https://doi.org/10.1109/iolts.2018.8474120
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2017 | Conference Paper | LibreCat-ID: 12973
Deshmukh, J., Kunz, W., Wunderlich, H.-J., & Hellebrand, S. (2017). Special Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE. https://doi.org/10.1109/vts.2017.7928933
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2017 | Misc | LibreCat-ID: 13078
Kampmann, M., & Hellebrand, S. (2017). X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz.
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2017 | Conference Paper | LibreCat-ID: 10576
Kampmann, M., & Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17). https://doi.org/10.1109/ddecs.2017.7934564
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2017 | Journal Article | LibreCat-ID: 29462
Sadeghi-Kohan, S., Kamal, M., & Navabi, Z. (2017). Self-Adjusting Monitor for Measuring Aging Rate and Advancement. IEEE Transactions on Emerging Topics in Computing, 8(3), 627–641. https://doi.org/10.1109/tetc.2017.2771441
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2017 | Conference Paper | LibreCat-ID: 29463
Jenihhin, M., Kamkin, A., Navabi, Z., & Sadeghi-Kohan, S. (2017). Universal mitigation of NBTI-induced aging by design randomization. 2016 IEEE East-West Design & Test Symposium (EWDTS). https://doi.org/10.1109/ewdts.2016.7807635
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2016 | Conference Paper | LibreCat-ID: 12975
Kampmann, M., & Hellebrand, S. (2016). X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In 25th IEEE Asian Test Symposium (ATS’16) (pp. 1–6). Hiroshima, Japan: IEEE. https://doi.org/10.1109/ats.2016.20
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2015 | Conference Paper | LibreCat-ID: 12976
Kampmann, M., A. Kochte, M., Schneider, E., Indlekofer, T., Hellebrand, S., & Wunderlich, H.-J. (2015). Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In 24th IEEE Asian Test Symposium (ATS’15) (pp. 109–114). Mumbai, India: IEEE. https://doi.org/10.1109/ats.2015.26
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2015 | Journal Article | LibreCat-ID: 13056
Huang, Z., Liang, H., & Hellebrand, S. (2015). A High Performance SEU Tolerant Latch. Journal of Electronic Testing - Theory and Applications (JETTA), 31(4), 349–359.
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2015 | Misc | LibreCat-ID: 13077
Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M., Liu, C., & Wunderlich, H.-J. (2015). Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany.
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2015 | Conference Paper | LibreCat-ID: 29465
Sadeghi-Kohan, S., Kamran, A., Forooghifar, F., & Navabi, Z. (2015). Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). https://doi.org/10.1109/dtis.2015.7127373
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2015 | Conference Paper | LibreCat-ID: 29466
Sadeghi-Kohan, S., Kamal, M., McNeil, J., Prinetto, P., & Navabi, Z. (2015). Online self adjusting progressive age monitoring of timing variations. 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). https://doi.org/10.1109/dtis.2015.7127368
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2014 | Conference Paper | LibreCat-ID: 12977
Hellebrand, S., Indlekofer, T., Kampmann, M., A. Kochte, M., Liu, C., & Wunderlich, H.-J. (2014). FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE. https://doi.org/10.1109/test.2014.7035360
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2014 | Journal Article | LibreCat-ID: 13054
Hellebrand, S., & Wunderlich, H.-J. (2014). SAT-Based ATPG beyond Stuck-at Fault Testing. DeGruyter Journal on Information Technology (It), 56(4), 165–172.
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2014 | Journal Article | LibreCat-ID: 13055
Rodriguez Gomez, L., Cook, A., Indlekofer, T., Hellebrand, S., & Wunderlich, H.-J. (2014). Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing - Theory and Applications (JETTA), 30(5), 527–540.
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2014 | Journal Article | LibreCat-ID: 46266
Alizadeh, B., Behnam, P., & Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers, 1–1. https://doi.org/10.1109/tc.2014.2329687
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2014 | Conference Paper | LibreCat-ID: 46268
Mohammadi, M., Sadeghi-Kohan, S., Masoumi, N., & Navabi, Z. (2014). An off-line MDSI interconnect BIST incorporated in BS 1149.1. 2014 19th IEEE European Test Symposium (ETS). https://doi.org/10.1109/ets.2014.6847847
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2014 | Conference Paper | LibreCat-ID: 46267
Sadeghi-Kohan, S., Behnam, P., Alizadeh, B., Fujita, M., & Navabi, Z. (2014). Improving polynomial datapath debugging with HEDs. 2014 19th IEEE European Test Symposium (ETS). https://doi.org/10.1109/ets.2014.6847797
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2013 | Conference Paper | LibreCat-ID: 12979
Hellebrand, S. (2013). Analyzing and Quantifying Fault Tolerance Properties. In 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE. https://doi.org/10.1109/latw.2013.6562662
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2013 | Misc | LibreCat-ID: 13075
Cook, A., Rodriguez Gomez, L., Hellebrand, S., Indlekofer, T., & Wunderlich, H.-J. (2013). Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina.
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2013 | Conference Paper | LibreCat-ID: 46271
Sadeghi-Kohan, S., Namaki-Shoushtari, M., Javaheri, F., & Navabi, Z. (2013). BS 1149.1 extensions for an online interconnect fault detection and recovery. 2012 IEEE International Test Conference. https://doi.org/10.1109/test.2012.6401583
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2013 | Conference Paper | LibreCat-ID: 46270
Sadeghi-Kohan, S., Keshavarz, S., Zokaee, F., Farahmandi, F., & Navabi, Z. (2013). A new structure for interconnect offline testing. East-West Design & Test Symposium (EWDTS 2013). https://doi.org/10.1109/ewdts.2013.6673207
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2012 | Conference Paper | LibreCat-ID: 12980
Cook, A., Hellebrand, S., E. Imhof, M., Mumtaz, A., & Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In 13th IEEE Latin American Test Workshop (LATW’12) (pp. 1–4). Quito, Ecuador: IEEE. https://doi.org/10.1109/latw.2012.6261229
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2012 | Conference Paper | LibreCat-ID: 12981
Cook, A., Hellebrand, S., & Wunderlich, H.-J. (2012). Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In 17th IEEE European Test Symposium (ETS’12) (pp. 1–6). Annecy, France: IEEE. https://doi.org/10.1109/ets.2012.6233025
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2012 | Misc | LibreCat-ID: 13074
Cook, A., Hellebrand, S., & Wunderlich, H.-J. (2012). Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany.
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2011 | Conference Paper | LibreCat-ID: 12982
Cook, A., Hellebrand, S., Indlekofer, T., & Wunderlich, H.-J. (2011). Diagnostic Test of Robust Circuits. In 20th IEEE Asian Test Symposium (ATS’11) (pp. 285–290). New Delhi, India: IEEE. https://doi.org/10.1109/ats.2011.55
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2011 | Conference Paper | LibreCat-ID: 12984
Polian, I., Becker, B., Hellebrand, S., Wunderlich, H.-J., & Maxwell, P. (2011). Towards Variation-Aware Test Methods. In 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE. https://doi.org/10.1109/ets.2011.51
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2011 | Conference Paper | LibreCat-ID: 13053
Cook, A., Hellebrand, S., Indlekofer, T., & Wunderlich, H.-J. (2011). Robuster Selbsttest mit Diagnose. In 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf” (pp. 48–53). Hamburg, Germany.
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2011 | Journal Article | LibreCat-ID: 13052
Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2011). Variation-Aware Fault Modeling. SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer, 54(4), 1813–1826.
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2011 | Conference Paper | LibreCat-ID: 46272
Kamran, A., Nemati, N., Sadeghi-Kohan, S., & Navabi, Z. (2011). Virtual tester development using HDL/PLI. 2010 East-West Design & Test Symposium (EWDTS). https://doi.org/10.1109/ewdts.2010.5742156
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2010 | Misc | LibreCat-ID: 10670
Fröse, V., Ibers, R., & Hellebrand, S. (2010). Testdatenkompression mit Hilfe der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany.
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2010 | Conference Paper | LibreCat-ID: 12987
Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE. https://doi.org/10.1109/dsnw.2010.5542612
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2010 | Conference Paper | LibreCat-ID: 13051
Hunger, M., & Hellebrand, S. (2010). Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf” (pp. 81–88). Wildbad Kreuth, Germany.
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2010 | Misc | LibreCat-ID: 13073
Hellebrand, S. (2010). Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180.
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2010 | Conference Paper | LibreCat-ID: 12983
Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Variation-Aware Fault Modeling. 19th IEEE Asian Test Symposium (ATS’10), 87–93. https://doi.org/10.1109/ats.2010.24
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2010 | Conference Paper | LibreCat-ID: 12985
Indlekofer, T., Schnittger, M., & Hellebrand, S. (2010). Efficient Test Response Compaction for Robust BIST Using Parity Sequences. 28th IEEE International Conference on Computer Design (ICCD’10), 480–485. https://doi.org/10.1109/iccd.2010.5647648
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2010 | Conference Paper | LibreCat-ID: 12986
Hunger, M., & Hellebrand, S. (2010). The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 101–108. https://doi.org/10.1109/dft.2010.19
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2010 | Conference Paper | LibreCat-ID: 12988
Froese, V., Ibers, R., & Hellebrand, S. (2010). Reusing NoC-Infrastructure for Test Data Compression. 28th IEEE VLSI Test Symposium (VTS’10), 227–231. https://doi.org/10.1109/vts.2010.5469570
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2010 | Conference Paper | LibreCat-ID: 13049
Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper).
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2010 | Conference Paper | LibreCat-ID: 13050
Indlekofer, T., Schnittger, M., & Hellebrand, S. (2010). Robuster Selbsttest mit extremer Kompaktierung. 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 17–24.
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2009 | Conference Paper | LibreCat-ID: 12991
Hunger, M., Hellebrand, S., Czutro, A., Polian, I., & Becker, B. (2009). ATPG-Based Grading of Strong Fault-Secureness. 15th IEEE International On-Line Testing Symposium (IOLTS’09. https://doi.org/10.1109/iolts.2009.5196027
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2009 | Conference Paper | LibreCat-ID: 12990
Hellebrand, S., & Hunger, M. (2009). Are Robust Circuits Really Robust? 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 77. https://doi.org/10.1109/dft.2009.28
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