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165 Publications


2019 | Conference Paper | LibreCat-ID: 12918
M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for Adaptive X-Handling,” in 50th IEEE International Test Conference (ITC), Washington, DC, USA, 2019, pp. 1–8.
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2018 | Misc | LibreCat-ID: 4576
A. Sprenger and S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.
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2018 | Journal Article | LibreCat-ID: 12974
S. Hellebrand, J. Henkel, A. Raghunathan, and H.-J. Wunderlich, “Guest Editors’ Introduction - Special Issue on Approximate Computing,” IEEE Embedded Systems Letters, vol. 10, no. 1, pp. 1–1, 2018.
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2018 | Journal Article | LibreCat-ID: 13057
M. Kampmann and S. Hellebrand, “Design For Small Delay Test - A Simulation Study,” Microelectronics Reliability, vol. 80, pp. 124–133, 2018.
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2018 | Misc | LibreCat-ID: 13072
M. Kampmann and S. Hellebrand, Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018.
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2018 | Conference Paper | LibreCat-ID: 29460
R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, and Z. Navabi, “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture,” 2018, doi: 10.1145/3194554.3194599.
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2018 | Conference Paper | LibreCat-ID: 4575
A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test,” 2018, doi: 10.1109/ddecs.2018.00020.
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2018 | Conference Paper | LibreCat-ID: 10575
C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, and H.-J. Wunderlich, “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention,” 2018, doi: 10.1109/ats.2018.00028.
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2018 | Conference Paper | LibreCat-ID: 29459
S. Sadeghi-Kohan, A. Vafaei, and Z. Navabi, “Near-Optimal Node Selection Procedure for Aging Monitor Placement,” 2018, doi: 10.1109/iolts.2018.8474120.
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2017 | Conference Paper | LibreCat-ID: 12973
J. Deshmukh, W. Kunz, H.-J. Wunderlich, and S. Hellebrand, “Special Session on Early Life Failures,” in 35th IEEE VLSI Test Symposium (VTS’17), 2017.
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2017 | Misc | LibreCat-ID: 13078
M. Kampmann and S. Hellebrand, X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz. 29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
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2017 | Conference Paper | LibreCat-ID: 10576
M. Kampmann and S. Hellebrand, “Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test,” 2017, doi: 10.1109/ddecs.2017.7934564.
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2017 | Journal Article | LibreCat-ID: 29462
S. Sadeghi-Kohan, M. Kamal, and Z. Navabi, “Self-Adjusting Monitor for Measuring Aging Rate and Advancement,” IEEE Transactions on Emerging Topics in Computing, vol. 8, no. 3, pp. 627–641, 2017, doi: 10.1109/tetc.2017.2771441.
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2017 | Conference Paper | LibreCat-ID: 29463
M. Jenihhin, A. Kamkin, Z. Navabi, and S. Sadeghi-Kohan, “Universal mitigation of NBTI-induced aging by design randomization,” 2017, doi: 10.1109/ewdts.2016.7807635.
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2016 | Conference Paper | LibreCat-ID: 12975
M. Kampmann and S. Hellebrand, “X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test,” in 25th IEEE Asian Test Symposium (ATS’16), 2016, pp. 1–6.
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2015 | Conference Paper | LibreCat-ID: 12976
M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, and H.-J. Wunderlich, “Optimized Selection of Frequencies for Faster-Than-at-Speed Test,” in 24th IEEE Asian Test Symposium (ATS’15), 2015, pp. 109–114.
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2015 | Journal Article | LibreCat-ID: 13056
Z. Huang, H. Liang, and S. Hellebrand, “A High Performance SEU Tolerant Latch,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 31, no. 4, pp. 349–359, 2015.
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2015 | Misc | LibreCat-ID: 13077
S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, and H.-J. Wunderlich, Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
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2015 | Conference Paper | LibreCat-ID: 29465
S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, and Z. Navabi, “Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation,” 2015, doi: 10.1109/dtis.2015.7127373.
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2015 | Conference Paper | LibreCat-ID: 29466
S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, and Z. Navabi, “Online self adjusting progressive age monitoring of timing variations,” 2015, doi: 10.1109/dtis.2015.7127368.
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2014 | Conference Paper | LibreCat-ID: 12977
S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, and H.-J. Wunderlich, “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects,” in IEEE International Test Conference (ITC’14), 2014.
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2014 | Journal Article | LibreCat-ID: 13054
S. Hellebrand and H.-J. Wunderlich, “SAT-Based ATPG beyond Stuck-at Fault Testing,” DeGruyter Journal on Information Technology (it), vol. 56, no. 4, pp. 165–172, 2014.
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2014 | Journal Article | LibreCat-ID: 13055
L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, and H.-J. Wunderlich, “Adaptive Bayesian Diagnosis of Intermittent Faults,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 30, no. 5, pp. 527–540, 2014.
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2014 | Journal Article | LibreCat-ID: 46266
B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs,” IEEE Transactions on Computers, pp. 1–1, 2014, doi: 10.1109/tc.2014.2329687.
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2014 | Conference Paper | LibreCat-ID: 46268
M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, and Z. Navabi, “An off-line MDSI interconnect BIST incorporated in BS 1149.1,” 2014, doi: 10.1109/ets.2014.6847847.
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2014 | Conference Paper | LibreCat-ID: 46267
S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, and Z. Navabi, “Improving polynomial datapath debugging with HEDs,” 2014, doi: 10.1109/ets.2014.6847797.
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2013 | Conference Paper | LibreCat-ID: 12979
S. Hellebrand, “Analyzing and Quantifying Fault Tolerance Properties,” in 14th IEEE Latin American Test Workshop - (LATW’13), 2013.
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2013 | Misc | LibreCat-ID: 13075
A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina, 2013.
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2013 | Conference Paper | LibreCat-ID: 46271
S. Sadeghi-Kohan, M. Namaki-Shoushtari, F. Javaheri, and Z. Navabi, “BS 1149.1 extensions for an online interconnect fault detection and recovery,” 2013, doi: 10.1109/test.2012.6401583.
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2013 | Conference Paper | LibreCat-ID: 46270
S. Sadeghi-Kohan, S. Keshavarz, F. Zokaee, F. Farahmandi, and Z. Navabi, “A new structure for interconnect offline testing,” 2013, doi: 10.1109/ewdts.2013.6673207.
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2012 | Conference Paper | LibreCat-ID: 12980
A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, and H.-J. Wunderlich, “Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test,” in 13th IEEE Latin American Test Workshop (LATW’12), 2012, pp. 1–4.
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2012 | Conference Paper | LibreCat-ID: 12981
A. Cook, S. Hellebrand, and H.-J. Wunderlich, “Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test,” in 17th IEEE European Test Symposium (ETS’12), 2012, pp. 1–6.
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2012 | Misc | LibreCat-ID: 13074
A. Cook, S. Hellebrand, and H.-J. Wunderlich, Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany, 2012.
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2011 | Conference Paper | LibreCat-ID: 12982
A. Cook, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, “Diagnostic Test of Robust Circuits,” in 20th IEEE Asian Test Symposium (ATS’11), 2011, pp. 285–290.
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2011 | Conference Paper | LibreCat-ID: 12984
I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, and P. Maxwell, “Towards Variation-Aware Test Methods,” in 16th IEEE European Test Symposium Trondheim (ETS’11), 2011.
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2011 | Conference Paper | LibreCat-ID: 13053
A. Cook, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, “Robuster Selbsttest mit Diagnose,” in 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit und Entwurf,” 2011, pp. 48–53.
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2011 | Journal Article | LibreCat-ID: 13052
F. Hopsch et al., “Variation-Aware Fault Modeling,” SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer, vol. 54, no. 4, pp. 1813–1826, 2011.
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2011 | Conference Paper | LibreCat-ID: 46272
A. Kamran, N. Nemati, S. Sadeghi-Kohan, and Z. Navabi, “Virtual tester development using HDL/PLI,” 2011, doi: 10.1109/ewdts.2010.5742156.
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2010 | Misc | LibreCat-ID: 10670
V. Fröse, R. Ibers, and S. Hellebrand, Testdatenkompression mit Hilfe der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
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2010 | Conference Paper | LibreCat-ID: 12987
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” in 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), 2010.
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2010 | Conference Paper | LibreCat-ID: 13051
M. Hunger and S. Hellebrand, “Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 81–88.
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2010 | Misc | LibreCat-ID: 13073
S. Hellebrand, Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180, 2010.
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2010 | Conference Paper | LibreCat-ID: 12983
F. Hopsch et al., “Variation-Aware Fault Modeling,” in 19th IEEE Asian Test Symposium (ATS’10), 2010, pp. 87–93, doi: 10.1109/ats.2010.24.
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2010 | Conference Paper | LibreCat-ID: 12985
T. Indlekofer, M. Schnittger, and S. Hellebrand, “Efficient Test Response Compaction for Robust BIST Using Parity Sequences,” in 28th IEEE International Conference on Computer Design (ICCD’10), 2010, pp. 480–485, doi: 10.1109/iccd.2010.5647648.
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2010 | Conference Paper | LibreCat-ID: 12986
M. Hunger and S. Hellebrand, “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems,” in 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 2010, pp. 101–108, doi: 10.1109/dft.2010.19.
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2010 | Conference Paper | LibreCat-ID: 12988
V. Froese, R. Ibers, and S. Hellebrand, “Reusing NoC-Infrastructure for Test Data Compression,” in 28th IEEE VLSI Test Symposium (VTS’10), 2010, pp. 227–231, doi: 10.1109/vts.2010.5469570.
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2010 | Conference Paper | LibreCat-ID: 13049
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” 2010.
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2010 | Conference Paper | LibreCat-ID: 13050
T. Indlekofer, M. Schnittger, and S. Hellebrand, “Robuster Selbsttest mit extremer Kompaktierung,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 17–24.
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2009 | Conference Paper | LibreCat-ID: 12991
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,” 2009, doi: 10.1109/iolts.2009.5196027.
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2009 | Conference Paper | LibreCat-ID: 12990
S. Hellebrand and M. Hunger, “Are Robust Circuits Really Robust?,” in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 2009, p. 77, doi: 10.1109/dft.2009.28.
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