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461 Publications
2026 | Journal Article | LibreCat-ID: 61152
Y. Umuroglu et al., “SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators,” ACM Transactions on Reconfigurable Technology and Systems, doi: 10.1145/3807510.
LibreCat
| DOI
2026 | Conference Paper | LibreCat-ID: 65501
L. Stasytis, F. Jentzsch, T. Preusser, Y. Umuroglu, J. Petri-Koenig, and Z. István, “Heuristic & Expert-Guided Buffer Sizing for Neural Network Inference Applications on FPGAs,” 2026, doi: 10.1109/icfpt67023.2025.00032.
LibreCat
| DOI
2026 | Conference Paper | LibreCat-ID: 65500
F. Jentzsch and M. Platzner, “Empirical QoR Estimation Flow for Fast Design Space Exploration of DNN Dataflow Accelerators,” 2026, doi: 10.1109/icfpt67023.2025.00044.
LibreCat
| DOI
2025 | Conference Paper | LibreCat-ID: 64112
F. Jalil, M. Awais, Q. A. Ahmed, H. G. Mohammadi, T. Jungeblut, and M. Platzner, “Deep&Wide: Achieving Area Efficiency in Scalable Approximate Accelerators,” 2025, doi: 10.1109/dsn-w65791.2025.00048.
LibreCat
| DOI
2025 | Conference Paper | LibreCat-ID: 64113
A. H. Hadipour, A. Jafari, M. Awais, and M. Platzner, “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation,” 2025, doi: 10.1109/ddecs63720.2025.11006769.
LibreCat
| DOI
2025 | Journal Article | LibreCat-ID: 62020
M. Awais, H. G. Mohammadi, and M. Platzner, “Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 9, pp. 2395–2405, 2025, doi: 10.1109/tvlsi.2025.3559377.
LibreCat
| DOI
2025 | Conference Paper | LibreCat-ID: 62019
A. H. Hadipour, A. Jafari, M. Awais, and M. Platzner, “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation,” 2025, doi: 10.1109/ddecs63720.2025.11006769.
LibreCat
| DOI
2025 | Mastersthesis | LibreCat-ID: 62268
P. Bengaluru Amarnath, Design and Integration of Intra-Process Communication for ROS 2 into ReconROS. Paderborn University, 2025.
LibreCat
2024 | Journal Article | LibreCat-ID: 52686
Q. A. Ahmed, T. Wiersema, and M. Platzner, “Post-configuration Activation of Hardware Trojans in FPGAs,” Journal of Hardware and Systems Security, 2024, doi: 10.1007/s41635-024-00147-5.
LibreCat
| DOI
2024 | Conference Paper | LibreCat-ID: 54468
M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing,” presented at the IEEE Computer Society Annual Symposium on VLSI, Knoxville, Tennessee, USA, 2024.
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