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403 Publications


2021 | Journal Article | LibreCat-ID: 27841
M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,” IEEE Access, doi: 10.1109/ACCESS.2021.3131213.
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2021 | Conference Paper | LibreCat-ID: 21610
M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual, 2021, pp. 27–32.
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2021 | Conference Paper | LibreCat-ID: 20681
Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,” in 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Alpexpo | Grenoble, France, 2021.
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2021 | Bachelorsthesis | LibreCat-ID: 22216
J. W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib. 2021.
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2021 | Conference Paper | LibreCat-ID: 22309
M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.
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2021 | Bachelorsthesis | LibreCat-ID: 22483
M. Brede, Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University, 2021.
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2021 | Conference Paper | LibreCat-ID: 21813
T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS,” in GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Lille, France.
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2021 | Mastersthesis | LibreCat-ID: 29540
M. A. Sheikh, Design and Implementation of a ReconROS-based Obstacle Avoidance System. Paderborn University, 2021.
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2021 | Preprint | LibreCat-ID: 22764 | OA
C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” arXiv:2107.07208. 2021.
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2021 | Conference Paper | LibreCat-ID: 21953
L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,” in Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference, doi: 10.1007/978-3-030-79025-7_4.
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