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385 Publications


2020 | Conference Paper | LibreCat-ID: 17063
T. Hansmeier, P. Kaufmann, and M. Platzner, “An Adaption Mechanism for the Error Threshold of XCSF,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 1756–1764.
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2020 | Conference Paper | LibreCat-ID: 16213
M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “A Hybrid Synthesis Methodology for Approximate Circuits,” in Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, Beijing, China, 2020, pp. 421–426.
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2020 | Conference Paper | LibreCat-ID: 21584
C. P. Gatica and M. Platzner, “Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures,” in Machine Learning for Cyber Physical Systems (ML4CPS 2017), 2020.
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2020 | Mastersthesis | LibreCat-ID: 21433
F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture. 2020.
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2019 | Preprint | LibreCat-ID: 16853
L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth Workshop on Approximate Computing (AxC 2019). .
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2019 | Journal Article | LibreCat-ID: 3585
L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Microelectronics Reliability, vol. 99, pp. 277–290, 2019.
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2019 | Conference Paper | LibreCat-ID: 9913
Q. A. Ahmed, T. Wiersema, and M. Platzner, “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan,” in Applied Reconfigurable Computing, Darmstadt, Germany, 2019, vol. 11444, pp. 127–136.
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2019 | Mastersthesis | LibreCat-ID: 15920
M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019.
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2019 | Mastersthesis | LibreCat-ID: 15874
C. Lienen, Implementing a Real-time System on a Platform FPGA operated with ReconOS. Universität Paderborn.
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2019 | Conference Paper | LibreCat-ID: 10577
L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19, Tysons Corner, VA, USA, 2019.
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2019 | Journal Article | LibreCat-ID: 11950
A. Boschmann, A. Agne, G. Thombansen, L. M. Witschen, F. Kraus, and M. Platzner, “Zynq-based acceleration of robust high density myoelectric signal processing,” Journal of Parallel and Distributed Computing, vol. 123, pp. 77–89, 2019.
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2019 | Journal Article | LibreCat-ID: 12871
M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum, 2019.
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2019 | Conference Paper | LibreCat-ID: 15422
N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on Nature and Biologically Inspired Computing (NaBIC), 2019.
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2019 | Mastersthesis | LibreCat-ID: 15883
S. Kumar Jeyakumar, Incremental learning with Support Vector Machine on embedded platforms. 2019.
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2019 | Mastersthesis | LibreCat-ID: 15946
J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip. 2019.
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2019 | Journal Article | LibreCat-ID: 12967
T. Hansmeier, M. Platzner, M. J. H. Pantho, and D. Andrews, “An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology,” Journal of Signal Processing Systems, vol. 91, no. 11, pp. 1259–1272, 2019.
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2019 | Mastersthesis | LibreCat-ID: 14831
N. S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University, 2019.
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2019 | Mastersthesis | LibreCat-ID: 14546
T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
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2018 | Dissertation | LibreCat-ID: 3720
N. Ho, FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018.
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2018 | Bachelorsthesis | LibreCat-ID: 1097
F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018.
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