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369 Publications


2011 | Conference Paper | LibreCat-ID: 2194
Meyer, B., Plessl, C., & Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In Symp. on Application Accelerators in High Performance Computing (SAAHPC) (pp. 60–63). IEEE Computer Society. https://doi.org/10.1109/SAAHPC.2011.12
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2011 | Book Chapter | LibreCat-ID: 2202
Plessl, C., & Platzner, M. (2011). Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In M. Khalgui & H.-M. Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility. Hershey, PA, USA: IGI Global. https://doi.org/10.4018/978-1-60960-086-0
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2011 | Conference Paper | LibreCat-ID: 666
Drzevitzky, S., & Platzner, M. (2011). Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach. In Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (pp. 58–65). https://doi.org/10.1109/ReCoSoC.2011.5981499
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2010 | Book Chapter | LibreCat-ID: 10704
Lübbers, E., & Platzner, M. (2010). ReconOS: An Operating System for Dynamically Reconfigurable Hardware. In M. Platzner, J. Teich, & N. Wehn (Eds.), Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications (pp. 269–290). Springer-Verlag GmbH. https://doi.org/10.1007/978-90-481-3485-4_13
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2010 | Conference Paper | LibreCat-ID: 13640
Giefers, H., & Platzner, M. (2010). A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. In Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL). IEEE.
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2010 | Conference (Editor) | LibreCat-ID: 2222
Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., & Stitt, G. (Eds.). (2010). Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.
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2010 | Mastersthesis | LibreCat-ID: 10642
Breitlauch, D. (2010). Evolvable Cache Controller. Paderborn University.
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2010 | Mastersthesis | LibreCat-ID: 10697
Knieper, T. (2010). Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University.
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2010 | Mastersthesis | LibreCat-ID: 10717
Niekamp, M. (2010). Transparente Hardwarebeschleunigung durch Shared Library Interposing. Paderborn University.
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2010 | Mastersthesis | LibreCat-ID: 10731
Runde, B. (2010). A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University.
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2010 | Conference Paper | LibreCat-ID: 13641
Schäfer, W., Birattari, M., Blömer, J., Dorigo, M., Engels, G., O’Grady, R., … Trächtler, A. (2010). Engineering Self-Coordinating Software Intensive Systems. In Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER) (pp. 321–324).
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2010 | Conference Paper | LibreCat-ID: 2216
Grad, M., & Plessl, C. (2010). Pruning the Design Space for Just-In-Time Processor Customization. In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) (pp. 67–72). Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/ReConFig.2010.19
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2010 | Conference Paper | LibreCat-ID: 2223
Lübbers, E., Platzner, M., Plessl, C., Keller, A., & Plattner, B. (2010). Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 225–231). CSREA Press.
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2010 | Conference Paper | LibreCat-ID: 2228
Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami & S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA).
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2010 | Journal Article | LibreCat-ID: 10605
Drzevitzky, S., Kastens, U., & Platzner, M. (2010). Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. International Journal of Reconfigurable Computing, 2010. https://doi.org/10.1155/2010/180242
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2010 | Mastersthesis | LibreCat-ID: 10629
Boschmann, A. (2010). EMG-basierte Ganganalyse. Paderborn University.
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2010 | Conference Paper | LibreCat-ID: 10686
Kaufmann, P., Knieper, T., & Platzner, M. (2010). A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers. In IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC) (pp. 541–548). IEEE.
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2010 | Book (Editor) | LibreCat-ID: 10763
Platzner, M., Teich, J., & Wehn, N. (Eds.). (2010). Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH. https://doi.org/10.1007/978-90-481-3485-4
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2010 | Conference Paper | LibreCat-ID: 13642
Giefers, H., & Platzner, M. (2010). A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics. In Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.
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2010 | Conference Paper | LibreCat-ID: 2224
Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking Facilities. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 144–150). CSREA Press.
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2010 | Conference Paper | LibreCat-ID: 10776
Khatir, M., Ghasemzadeh Mohammadi, H., & Ejlali, A. (2010). Sub-threshold charge recovery circuits. In Computer Design (ICCD), 2010 IEEE International Conference on (pp. 138–144). IEEE. https://doi.org/10.1109/ICCD.2010.5647815
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2010 | Bachelorsthesis | LibreCat-ID: 10649
Dridger, D. (2010). Soft Microprocessors with tightly coupled Application-Specific Coprocessors. Paderborn University.
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2010 | Journal Article | LibreCat-ID: 10694
Kebschull, U., Platzner, M., & Teich, J. (2010). Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial). IET Computers Digital Techniques, 4(3), 157–158. https://doi.org/10.1049/iet-cdt.2010.9044
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2010 | Conference Paper | LibreCat-ID: 10699
Knieper, T., Kaufmann, P., Glette, K., Platzner, M., & Torresen, J. (2010). Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture. In IEEE Intl. Conf. on Evolvable Systems (ICES) (Vol. 6274, pp. 250–261). Springer.
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2010 | Mastersthesis | LibreCat-ID: 10752
Wiersema, T. (2010). Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University.
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2010 | Conference Paper | LibreCat-ID: 2206
Keller, A., Plattner, B., Lübbers, E., Platzner, M., & Plessl, C. (2010). Reconfigurable Nodes for Future Networks. In Proc. IEEE Globecom Workshop on Network of the Future (FutureNet) (pp. 372–376). IEEE. https://doi.org/10.1109/GLOCOMW.2010.5700341
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2010 | Conference Paper | LibreCat-ID: 2220
Andrews, D., & Plessl, C. (2010). Configurable Processor Architectures: History and Trends. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (p. 165). CSREA Press.
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2010 | Conference Paper | LibreCat-ID: 10683
Kaufmann, P., Englehart, K., & Platzner, M. (2010). Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms. In International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) (pp. 6357–6360). IEEE.
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2010 | Mastersthesis | LibreCat-ID: 10710
Meiche, R. (2010). FPGA/CPU Multicore-Plattform für ReconOS/eCos. Paderborn University.
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2010 | Mastersthesis | LibreCat-ID: 10614
Agne, A. (2010). Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University.
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2010 | Bachelorsthesis | LibreCat-ID: 10657
Graf, T. (2010). Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University.
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2010 | Conference Paper | LibreCat-ID: 2226
Beisel, T., Niekamp, M., & Plessl, C. (2010). Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 65–72). IEEE Computer Society. https://doi.org/10.1109/ASAP.2010.5540798
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2009 | Conference Paper | LibreCat-ID: 10639
Boschmann, A., Kaufmann, P., Platzner, M., & Winkler, M. (2009). Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets. In Proc. Technically Assisted Rehabilitation (TAR).
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2009 | Conference Paper | LibreCat-ID: 13638
Happe, M., Lübbers, E., & Platzner, M. (2009). An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/fpt.2009.5377645
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2009 | Conference Paper | LibreCat-ID: 13634
Giefers, H., & Platzner, M. (2009). Towards Models for Many-Cores: The Case for the Reconfigurable Mesh. In Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS).
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2009 | Conference Paper | LibreCat-ID: 13639
Drzevitzky, S., Kastens, U., & Platzner, M. (2009). Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.
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2009 | Conference Paper | LibreCat-ID: 2350
Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 275–278). IEEE Computer Society. https://doi.org/10.1109/FCCM.2009.25
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2009 | Conference Paper | LibreCat-ID: 2261
Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (pp. 338–344). IEEE.
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2009 | Mastersthesis | LibreCat-ID: 10749
Warkentin, A. (2009). Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units. Paderborn University.
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2009 | Conference Paper | LibreCat-ID: 13635
Giefers, H., & Platzner, M. (2009). ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores. In Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium. IEEE.
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2009 | Conference Paper | LibreCat-ID: 2262
Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS) (pp. 11–18). Los Alamitos, CA, USA: IEEE Computer Society.
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2009 | Mastersthesis | LibreCat-ID: 10702
Kostin, A. (2009). Evolvable Robot Controller. Paderborn University.
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2009 | Conference Paper | LibreCat-ID: 13636
Lübbers, E., & Platzner, M. (2009). Cooperative Multithreading in Dynamically Reconfigurable Systems. In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE.
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2009 | Conference Paper | LibreCat-ID: 2263
Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 319–322). USA: CSREA Press.
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2009 | Conference Paper | LibreCat-ID: 10777
Ghasemzadeh Mohammadi, H., Miremadi, S. G., & Ejlali, A. (2009). Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors. In Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on (pp. 252–255). IEEE. https://doi.org/10.1109/PRDC.2009.69
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2009 | Journal Article | LibreCat-ID: 10703
Lübbers, E., & Platzner, M. (2009). ReconOS: Multithreaded Programming for Reconfigurable Computers. ACM Transactions on Embedded Computing Systems, 9(1), 8:1-8:33. https://doi.org/10.1145/1596532.1596540
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2009 | Mastersthesis | LibreCat-ID: 10746
Tofall, M. (2009). Compiler for a Custom Instruction Set CPU. Paderborn University.
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2009 | Bachelorsthesis | LibreCat-ID: 10753
Wildenhain, B. (2009). Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS. Paderborn University.
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2009 | Conference Paper | LibreCat-ID: 13632
Happe, M., Lübbers, E., & Platzner, M. (2009). A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC). Springer.
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2009 | Conference Paper | LibreCat-ID: 13637
Giefers, H., & Platzner, M. (2009). Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) . IEEE.
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